參數(shù)資料
型號(hào): ADUC7060BCPZ32-RL
廠商: Analog Devices Inc
文件頁數(shù): 52/108頁
文件大?。?/td> 0K
描述: IC MCU FLASH 24BIT 32KB 48LFCSP
設(shè)計(jì)資源: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 32
電壓 - 電源 (Vcc/Vdd): 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x24b,8x24b,D/A 1x14b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 48 of 108
Bit
Name
Description
7
NOTCH2
Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
fNOTCH2
= 1.333 × fNOTCH
where fNOTCH is the location of the first notch in the response.
6:0
SF[6:0]
Sinc3 decimation factor (SF).1 The value (SF) written in these bits controls the oversampling (decimation factor) of the
sinc3 filter. The output rate from the sinc3 filter is given by
fADC
= (512,000/([SF + 1] × 64)) Hz2
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, fADC is forced to 60 Hz.
For SF = 127, fADC is forced to 50 Hz.
For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 46.
1
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
2
In low power mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided by 4 (approximately).
Table 46. ADC Conversion Rates and Settling Times
Chop
Enabled
Averaging
Factor
Running
Average
fADC Normal Mode
fADC Low Power Mode
tSETTLING1
No
64
]
1
[
000
,
512
×
+
SF
64
]
1
[
072
,
131
×
+
SF
ADC
f
3
No
Yes
64
]
1
[
000
,
512
×
+
SF
64
]
1
[
072
,
131
×
+
SF
ADC
f
4
No
Yes
No
]
3
[
64
]
1
[
000
,
512
AF
SF
+
×
+
]
3
[
64
]
1
[
072
,
131
AF
SF
+
×
+
ADC
f
1
No
Yes
]
3
[
64
]
1
[
000
,
512
AF
SF
+
×
+
]
3
[
64
]
1
[
072
,
131
AF
SF
+
×
+
ADC
f
2
Yes
N/A
3
]
3
[
64
]
1
[
000
,
512
+
×
+
AF
SF
3
]
3
[
64
]
1
[
072
,
131
+
×
+
AF
SF
ADC
f
2
1
An additional time of approximately 60 s per ADC is required before the first ADC is available.
Table 47. Allowable Combinations of SF and AF
AF Range
SF
0
1 to 7
8 to 63
0 to 31
Yes
32 to 63
Yes
No
64 to 127
Yes
No
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