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參數(shù)資料
| 型號(hào)： | ADUC7060BCPZ32-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 97/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 24BIT 32KB 48LFCSP |
| 設(shè)計(jì)資源： | 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 14 |
| 程序存儲(chǔ)器容量： | 32KB（16K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 89 of 108
I2C Master Status, I2CMSTA, Register
Name:
I2CMSTA
Address:
0xFFFF0904
Default value:
0x0000
Access:
Read only
Function:
This 16-bit MMR is the I2C status register in master mode.
Table 98. I2CMSTA MMR Bit Designations
Bit
Name
Description
15:11
Reserved. These bits are reserved.
10
I2CBBUSY
I2C bus busy status bit.
This bit is set to 1 when a start condition is detected on the I2C bus.
This bit is cleared when a stop condition is detected on the bus.
9
I2CMRxFO
Master receive FIFO overflow.
This bit is set to 1 when a byte is written to the receive FIFO when it is already full.
This bit is cleared in all other conditions.
8
I2CMTC
I2C transmission complete status bit.
This bit is set to 1 when a transmission is complete between the master and the slave with which it was
communicating. If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
Clear this interrupt source.
7
I2CMNA
I2C master no acknowledge data bit
This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If
the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
6
I2CMBUSY
I2C master busy status bit.
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
5
I2CAL
I2C arbitration lost status bit.
This bit is set to 1 when the I2C master does not gain control of the I2C bus. If the I2CALENI bit in I2CMCON is set, an
interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
4
I2CMNA
I2C master no acknowledge address bit.
This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the
I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
3
I2CMRXQ
I2C master receive request bit.
This bit is set to 1 when data enters the receive FIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated.
This bit is cleared in all other conditions.
2
I2CMTXQ
I2C master transmit request bit.
This bit goes high if the transmit FIFO is empty or contains only one byte and the master has transmitted an address
+ write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
1:0
I2CMTFSTA
I2C master transmit FIFO status bits.
[00] = I2C master transmit FIFO empty.
[01] = 1 byte in master transmit FIFO.
[10] = 1 byte in master transmit FIFO.
[11] = I2C master transmit FIFO full.
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