參數(shù)資料
型號: ADUC7060BCPZ32-RL
廠商: Analog Devices Inc
文件頁數(shù): 53/108頁
文件大?。?/td> 0K
描述: IC MCU FLASH 24BIT 32KB 48LFCSP
設計資源: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標準包裝: 2,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 32
電壓 - 電源 (Vcc/Vdd): 2.375 V ~ 2.625 V
數(shù)據(jù)轉換器: A/D 5x24b,8x24b,D/A 1x14b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 49 of 108
ADC Configuration Register
Name:
ADCCFG
Address:
0xFFFF0518
Default value:
0x00
Access:
Read and write
Function:
The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Table 48. ADCCFG MMR Bit Designations
Bit
Name
Description
7
GNDSW_EN
Analog ground switch enable.
This bit is set to 1 by user software to connect the external GND_SW pin to an internal analog ground
reference point. This bit can be used to connect and disconnect external circuits and components to ground
under program control and thereby minimize dc current consumption when the external circuit or
component is not being used. This bit is used in conjunction with ADCCFG[1] to select a 20 k resistor to
ground.
When this bit is cleared, the analog ground switch is disconnected from the external pin.
6:5
ADC0ACCEN[1:0]
Primary channel (32-bit) accumulator enable.
[00] = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion
(ADCSTA[0] set twice) before the accumulator can be re-enabled to ensure that the accumulator is reset.
[01] = accumulator active. Positive current values are added to the accumulator total; the accumulator can
overflow if allowed to run for >65,535 conversions. Negative current values are subtracted from the
accumulator total; the accumulator is clamped to a minimum value of 0.
[10] = accumulator active. Same as [01] except that there is no clamp. Positive current values are added to the
accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. The absolute
values of negative current are subtracted from the accumulator total; the accumulator in this mode continues
to accumulate negatively, below 0.
[11] = accumulator and comparator active. This causes an ADC0 interrupt if ADCMSKI[6] is set.
4:3
ADC0CMPEN[1:0]
Primary ADC comparator enable bits.
[00] = comparator disabled.
[01] = comparator active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH.
[10] = comparator count mode active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥
ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH resets the threshold
counter value (ADC0THV) to 0.
[11] = comparator count mode active, interrupt asserted if absolute value of ADC0 conversion result |I| ≥
ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH decrements the threshold
counter value (ADC0THV) toward 0.
2
ADC0OREN
ADC0 overrange enable.
Set by the user to enable a coarse comparator on the primary channel ADC. If the reading is grossly (>30%
approximate) overrange for the active gain setting, the overrange bit in the ADCSTA MMR is set. The ADC
reading must be outside this range for greater than 125 s for the flag to be set.
Do not use this feature in ADC low power mode.
1
GNDSW_RES_EN
Set to 1 to enable a 20 k resistor in series with the ground switch.
Clear this bit to disable this resistor.
0
ADCRCEN
ADC result counter enable.
Set by user to enable the result count mode. ADC interrupts occur if ADC0RCR = ADC0RCV.
Cleared to disable the result counter. ADC interrupts occur after every conversion.
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