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參數(shù)資料
| 型號(hào)： | ADUC7060BCPZ32-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 94/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 24BIT 32KB 48LFCSP |
| 設(shè)計(jì)資源： | 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 14 |
| 程序存儲(chǔ)器容量： | 32KB（16K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 86 of 108
I2C
Each ADuC706x incorporates an I2C peripheral that can be
configured as a fully I2C-compatible I2C bus master device or
as a fully I2C bus-compatible slave device. The two pins used for
data transfer, SDA and SCL, are configured in a wire-AND’ed
format that allows arbitration in a multimaster system. These
pins require external pull-up resistors. Typical pull-up resistor
values are between 4.7 k and 10 k.
Users program the I2C bus peripheral (addressed in the I2C bus
system). This ID can be modified any time that a transfer is not
in progress. The user can configure the interface to respond to
four slave addresses.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I2C peripheral can be configured only as a master or a slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes.
The I2C interface on the ADuC706x includes the following
features:
Support for repeated start conditions. In master mode, the
ADuC706x can be programmed to generate a repeated
start. In slave mode, the ADuC706x recognizes repeated
start conditions.
In master and slave modes, the part recognizes both 7-bit
and 10-bit bus addresses.
In I2C master mode, the ADuC706x supports continuous
reads from a single slave up to 512 bytes in a single transfer
sequence.
Clock stretching is supported in both master and slave
modes.
In slave mode, the ADuC706x can be programmed to
return a no acknowledge (NACK). This allows the
validation of checksum bytes at the end of I2C transfers.
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I2C hardware testing.
The transmit and receive circuits in both master and slave
modes contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
CONFIGURING EXTERNAL PINS FOR I2C
FUNCTIONALITY
The I2C functions of the P0.1/SCLK/SCL and P0.3/MOSI/SDA
pins of the ADuC706x device are P0.1 and P0.3. The function of
P0.1 is the I2C clock signal (SCL) and the function of P0.3 is the
I2C data signal (SDA). To configure P0.1 and P0.3 for I2C mode,
Bit 4 and Bit 12 of the GP0CON0 register must be set to 1. Bit 1
of the GP0CON1 register must also be set to 1 to enable I2C
mode.
Note that, to write to GP0CON1, the GP0KEY1 register must
be set to 0x7 immediately before writing to GP0CON1. Also,
the GP0KEY2 register must be set to 0x13 immediately after
writing to GP0CON1. The following code example shows this
in detail:
GP0CON0 = BIT4 + BIT12;
// Select SPI/I
2C alternative function for P0.1 and P0.3
GP0KEY1 = 0x7;
// Write to GP0KEY1
GP0CON1 = BIT1;
// Select I
2C functionality for P0.1 and P0.3
GP0KEY2 = 0x13;
// Write to GP0KEY2
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