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| 型號： | ADUC7122BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7TDMI MCU 126KB 108CSPBGA |
| 特色產(chǎn)品： | ADuC7122 Precision Analog Microcontroller |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x12b，D/A 12x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -10°C ~ 95°C |
| 封裝/外殼： | 108-LFBGA，CSPBGA |
| 包裝： | 托盤 |
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ADuC7122
Rev. 0 | Page 28 of 96
ADC TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is
0 V to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with
1 LSB = FS/4096 or
2.5 V/4096 = 0.61 mV or
610 μV when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS – 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 13.
O
U
T
P
UT
CO
DE
VOLTAGE INPUT
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
1LSB
0V
+FS – 1LSB
0000 0000 0010
0000 0000 0001
0000 0000 0000
1LSB =
FS
4096
0
875
5-
0
13
Figure 13. ADC Transfer Function in Pseudo Differential Mode or
Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN inputs (that is, VIN+
VIN) of the currently enabled differential channel. The maxi-
mum amplitude of the differential signal is, therefore, VREF to
+VREF p-p (2 × VREF). This is regardless of the common mode
(CM). The common mode is the average of the two signals
(VIN+ + VIN)/2, and is, therefore, the voltage that the two inputs
are centered on. This results in the span of each input being CM
± VREF/2. This voltage must be set up externally, and its range
The output coding is twos complement in fully differential
mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV
when VREF = 2.5 V. The output result is ±11 bits, but this is
shifted by one to the right, which allows the result in ADCDAT
to be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 14.
O
U
T
P
UT
CO
DE
VOLTAGE INPUT (VIN+ – VIN–)
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0001
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
–VREF + 1LSB
+VREF – 1LSB
0LSB
1LSB =
2 × VREF
4096
SIGN
BIT
08
75
5-
0
14
Figure 14. ADC Transfer Function in Differential Mode
ADC Input Channels
The ADuC7122 provides 11 fixed gain ADC input pins. Each of
these pins can be separately configured as a differential input
pair, single-ended input, or positive side pseudo differential input
(the negative side must be the AINCM channel). The buffer and
ADC are configured independently from input channel selec-
tion. Note that the input range of the ADC input buffer is from
0.15 V to AVDD 0.15 V. If the input signal range exceeds this
range, the input buffer must be bypassed.
The ADC mux can be configured to select an internal channel
like IOVDD_MON or the temperature sensor. When convert-
ing on an internal channel, the input buffer must be enabled.
In addition, an on-chip diode can be selected to provide chip
temperature monitoring. The ADC can also select VREF and
AGND as the input for calibration purposes.
PGA and Input Buffer
The ADuC7122 contains two programmable gain channels that
operate in pseudo differential mode. The PGA is a one-stage
positive gain amplifier that is able to accept an input from 0.1 V
to AVDD 1.2 V. The PGA output can swing up to 2.5 V. The
PGA is designed to handle 10 mV minimum input.
The gain of the PGA is from 1 to 5 with 32 linear steps. The
PGA cannot be bypassed for the PADC0 and PADC1 channels.
The PGAs use a PMOS input to minimize nonlinearity and
noise. The input level for PGA is limited from AVDD 1.2 V to
0.1 V to make sure the amplifiers are not saturated. The input
buffer is a rail-to-rail buffer. It can accept signals from 0.15 V
to AVDD 0.15 V. Each of the input buffers can be bypassed
independently.
To minimize noise, the PADC input buffer can be bypassed.
PADCxN is driven by a buffer to 0.15 V to keep the PGA from
saturation when the input current drops to 0. The buffer can be
disabled by setting ADCCON[14] so that the PADCxN can be
connected to GND as well.
The PADCx channels are only specified to operate in pseudo
differential mode and this assumes the negative input is close
to ground.
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