參數(shù)資料
型號： ADUC7122BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 36/96頁
文件大?。?/td> 0K
描述： IC ARM7TDMI MCU 126KB 108CSPBGA
特色產(chǎn)品： ADuC7122 Precision Analog Microcontroller
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b，D/A 12x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 托盤
ADuC7122
Rev. 0 | Page 41 of 96
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 26.
08
755
-02
7
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES
0x00000020
0x00041FFF
0x0009F800
0xFFFFFFFF
FLASH/EE
SRAM
MIRROR SPACE
0x00000000
0x00040000
0x00080000
Figure 26. Remap for Exception Execution
By default and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, facilitating execution of exception routines from SRAM
instead of from Flash/EE. This means exceptions are executed
twice as fast, with the exception being executed in ARM mode
(32 bits), and the SRAM being 32 bits wide instead of a 16-bit
wide Flash/EE memory.
Remap Operation
When a reset occurs on the ADuC7122, execution starts
automatically in factory-programmed internal configuration
code. This kernel is hidden and cannot be accessed by user
code. If the ADuC7122 is in normal mode (the BM pin is high),
it executes the power-on configuration routine of the kernel
and then jumps to the reset vector Address 0x00000000 to
execute the reset exception routine of the user. Because the
Flash/EE is mirrored at the bottom of the memory array at
reset, the reset interrupt routine must always be written in
Flash/EE.
The memory remap from Flash/EE is configured by setting Bit 0 of
the REMAP register. Precautions must be taken to execute this
command from Flash/EE, above Address 0x00080020, and not
from the bottom of the array because this is replaced by the SRAM.
This operation is reversible: the Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Precaution must again be taken to execute the remap function
from outside the mirrored area. Any kind of reset remaps the
Flash/EE memory at the bottom of the array.
Reset Operation
There are four types of reset: external reset, power-on reset,
watchdog expiration, and software force reset. The RSTSTA
register indicates the source of the last reset and RSTCLR clears
the RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset. If
RSTSTA is null, the reset was external. Note that when clearing
RSTSTA, all bits that are currently 1 must be cleared. Other-
wise, a reset event occurs.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
Table 60. REMAP MMR Bit Designations (Address = 0xFFFF0220, Default Value = 0x00)
Bit
Name
Description
0
Remap
Remap bit.
Set by the user to remap the SRAM to Address 0x00000000.
Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000.
Table 61. RSTSTA MMR Bit Designations (Address = 0xFFFF0230, Default Value = 0x0X)
Bit
Description
7:3
Reserved.
2
Software reset.
Set by the user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
1
Watchdog timeout.
Set automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-on reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
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