參數(shù)資料
型號(hào)： ADUC7122BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 76/96頁(yè)
文件大小： 0K
描述： IC ARM7TDMI MCU 126KB 108CSPBGA
特色產(chǎn)品： ADuC7122 Precision Analog Microcontroller
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b，D/A 12x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 托盤
ADuC7122
Rev. 0 | Page 78 of 96
FIQEN
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an FIQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked, which does not
create an FIQ exception. The FIQEN register cannot be used to
disable an interrupt.
FIQEN Register
Name:
FIQEN
Address:
0xFFFF0108
Default Value:
0x00000000
Access:
Read/write
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the FIQEN register without
affecting the remaining bits. The pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
FIQCLR Register
Name:
FIQCLR
Address:
0xFFFF010C
Default Value:
0x00000000
Access:
Write only
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default Value:
0x00000000
Access:
Read only
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG,
described in Table 129. This MMR allows the control of a
programmed source interrupt.
Table 129. SWICFG MMR Bit Designations
Bit
Description
31 to 3
Reserved.
2
Programmed Interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
1
Programmed Interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
0
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time to be detected by the interrupt controller
and by the user in the IRQSTA/FIQSTA register.
08
75
5-
0
37
POINTER TO
FUNCTION
(IRQVEC)
IRQ_SOURCE
FIQ_SOURCE
PROGRAMMABLE PRIORITY
PER INTERRUPT (IRQP0/IRQP1/IRQP2)
INTERNAL
ARBITER
LOGIC
INTERRUPT VECTOR
BIT 31 TO
BIT 23
UNUSED
BIT 1 TO
BIT 0
LSB
BIT 22 TO BIT 7
(IRQBASE)
BIT 6 TO
BIT 2
HIGHEST
PRIORITY
ACTIVE IRQ
Figure 36. Interrupt Structure
Vectored Interrupt Controller (VIC)
The ADuC7122 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Vectored interrupts—allow a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. Therefore, if the VIC is enabled
for both the FIQ and IRQ and prioritization is maximized,
then it is possible to have 16 separate interrupt levels.
Programmable interrupt priorities—using the IRQP0 to
IRQP2 registers, an interrupt source can be assigned an
interrupt priority level value between 1 and 8.
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