2.5 V reference, T
參數(shù)資料
型號: ADUC7122BBCZ
廠商: Analog Devices Inc
文件頁數(shù): 78/96頁
文件大?。?/td> 0K
描述: IC ARM7TDMI MCU 126KB 108CSPBGA
特色產(chǎn)品: ADuC7122 Precision Analog Microcontroller
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b,D/A 12x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 托盤
ADuC7122
Rev. 0 | Page 8 of 96
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed Up To
4
kV
FCIDM Passed Up To
0.5
kV
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Applies to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN); see the the Calibration section.
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage, as shown in Figure 23. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC Circuit Overview
section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 VREF calibration and trimming are performed with core operating in normal mode (CD = 0), ADC on, and all DACs on. VREF accuracy may vary under other operating
conditions.
8 DAC linearity is calculated using a reduced code range of 100 to 3995.
9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
10 Die temperature.
11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at 40°C, +25°C, +85°C, and +125°C.
12 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
13 Test carried out with a maximum of eight I/Os set to a low output level.
14 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
15 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
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