參數(shù)資料
型號： ADUC848BCPZ62-5
廠商： Analog Devices Inc
文件頁數(shù)： 14/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/16BIT ADC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 13 of 108
Pin No:
52-MQFP
Pin No:
56-LFCSP
Mnemonic
Type1
Description
20, 34, 48
22, 36, 51
DVDD
S
Digital Supply Voltage.
21, 35, 47
23, 37, 38, 50
DGND
S
Digital Ground.
26
28
SCLK (I2C)
I/O
Serial Interface Clock for the I2C Interface. As an input, this pin is a Schmitt-
triggered input. A weak internal pull-up is present on this pin unless it is
outputting logic low. This pin can also be controlled in software as a digital
output pin.
27
29
SDATA
I/O
Serial Data Pin for the I2C Interface. As an input, this pin has a weak internal
pull-up present unless it is outputting logic low.
28–31,
36–39
30–33, 39–
42
P2.0–P2.7
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that
have 1s written to them are pulled high by the internal pull-up resistors, and
in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low source current because of the internal pull-up resistors. Port 2
emits the middle and high-order address bytes during accesses to the 24-bit
external data memory space.
Port 2 pins also have the various secondary functions described below.
28
30
P2.0/SCLOCK (SPI)
Serial Interface Clock for the SPI Interface. As an input this pin is a Schmitt-
triggered input. A weak internal pull-up is present on this pin unless it is
outputting logic low.
29
31
P2.1/MOSI
Serial Master Output/Slave Input Data for the SPI Interface. A strong internal
pull-up is present on this pin when the SPI interface outputs a logic high. A
strong internal pull-down is present on this pin when the SPI interface
outputs a logic low.
30
32
P2.2/MISO
Master Input/Slave Output for the SPI Interface. A weak pull-up is present on
this input pin.
31
33
P2.3/SS/T2
Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
For both package options, this pin can also be used to provide a clock input to
Timer 2. When enabled, Counter 2 is incremented in response to a negative
transition on the T2 input pin.
36
39
P2.4/T2EX
Control Input to Timer 2. When enabled, a negative transition on the T2EX
input pin causes a Timer 2 capture or reload event.
37
40
P2.5/PWM0
If the PWM is enabled, the PWM0 output appears at this pin.
38
41
P2.6/PWM1
If the PWM is enabled, the PWM1 output appears at this pin.
39
42
P2.7/PWMCLK
If the PWM is enabled, an external PWM clock can be provided at this pin.
32
34
XTAL1
I
Input to the Crystal Oscillator Inverter.
33
35
XTAL2
O
Output from the Crystal Oscillator Inverter. See the Hardware Design
Considerations section for a description.
40
43
EA
External Access Enable, Logic Input. When held high, this input enables the
device to fetch code from internal program memory locations 0000H to
F7FFH. No external program memory access is available on the ADuC845,
ADuC847, or ADuC848. To determine the mode of code execution, the EA pin
is sampled at the end of an external RESET assertion or as part of a device
power cycle. EA can also be used as an external emulation I/O pin, and
therefore the voltage level at this pin must not be changed during normal
operation because this might cause an emulation interrupt that halts code
execution.
41
44
PSEN
O
Program Store Enable, Logic Output. This function is not used on the
ADuC845, ADuC847, or ADuC848. This pin remains high during internal
program execution.
PSEN can also be used to enable serial download mode when pulled low
through a resistor at the end of an external RESET assertion or as part of a
device power cycle.
42
45
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte
(and page byte for 24-bit data address space accesses) of the address to
external memory during external data memory access cycles. It can be
disabled by setting the PCON.4 bit in the PCON SFR.
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