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| 型號： | ADUC848BCPZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH W/16BIT ADC 56LFCSP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x16b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 34 of 108
enabled for any SF word that yields an ADC throughput that is
less than 20 Hz with chop enabled (SF ≥ 68 decimal).
ADC CHOPPING
The ADCs on the ADuC845/ADuC847/ADuC848 implement a
chopping scheme whereby the ADC repeatedly reverses its
inputs. The decimated digital output words from the Sinc3 filter,
therefore, have a positive and negative offset term included. As
a result, a final summing stage is included in each ADC so that
each output word from the filter is summed and averaged with
the previous filter output to produce a new valid output result
to be written to the ADC data SFRs. The ADC throughput or
update rate is listed in Table 29. The chopping scheme incor-
porated into the parts results in excellent dc offset and offset
drift specifications, and is extremely beneficial in applications
where drift, noise rejection, and optimum EMI performance are
important. ADC chop can be disabled via the chop bit in the
ADCMODE SFR (ADCMODE.3). Setting this bit to 1 (logic
high) disables chop mode.
CALIBRATION
The ADuC845/ADuC847/ADuC848 incorporate four calibration
modes that can be programmed via the mode bits in the
ADCMODE SFR detailed in Table 24. Every part is calibrated
before it leaves the factory. The resulting offset and gain
calibration coefficients for both the primary and auxiliary
(ADuC845 only) ADCs are stored on-chip in manufacturing-
specific Flash/EE memory locations. At power-on or after a
reset, these factory calibration registers are automatically
downloaded to the ADC calibration registers in the part’s SFR
space. To facilitate user calibration, each of the primary and
auxiliary (ADuC845 only) ADCs have dedicated calibration
control SFRs, which are described in the ADC SFR Interface
section. Once a user initiates a calibration procedure, the factory
calibration values that were initially downloaded during the
power-on sequence to the ADC calibration SFRs are overwritten.
The ADC to be calibrated must be enabled via the ADC enable
bits in the ADCMODE register.
Even though an internal offset calibration mode is described in
this section, note that the ADCs can be chopped. This chopping
scheme inherently minimizes offset errors and means that an
offset calibration should never be required. Also, because
factory 5 V/25°C gain calibration coefficients are automatically
present at power-on, an internal full-scale calibration is required
only if the part is operated at 3 V or at temperatures significantly
different from 25°C.
If the part is operated in chop disabled mode, a calibration may
need to be done with every gain range change that occurs via
the PGA.
The ADuC845/ADuC847/ADuC848 each offer internal or
system calibration facilities. For full calibration to occur on the
selected ADC, the calibration logic must record the modulator
output for two input conditions: zero-scale and full-scale points.
These points are derived by performing a conversion on the
different input voltages (zero-scale and full-scale) provided to the
input of the modulator during calibration. The result of the
zero-scale calibration conversion is stored in the offset
calibration registers for the appropriate ADC. The result of the
full-scale calibration conversion is stored in the gain calibration
registers for the appropriate ADC. With these readings, the
calibration logic can calculate the offset and the gain slope for
the input-to-output transfer function of the converter.
During an internal zero-scale or full-scale calibration, the
respective zero-scale input or full-scale input is automatically
connected to the ADC inputs internally. A system calibration,
however, expects the system zero-scale and system full-scale
voltages to be applied externally to the ADC pins by the user
before the calibration mode is initiated. In this way, external
errors are taken into account and minimized. Note that all
ADuC845/ADuC847/ADuC848 ADC calibrations are carried
out at the user-selected SF word update rate. To optimize
calibration accuracy, it is recommended that the slowest possible
update rate be used.
Internally in the parts, the coefficients are normalized before
being used to scale the words coming out of the digital filter.
The offset calibration coefficient is subtracted from the result
prior to the multiplication by the gain coefficient.
From an operational point of view, a calibration should be
treated just like an ordinary ADC conversion. A zero-scale
calibration (if required) should always be carried out before a
full-scale calibration. System software should monitor the
relevant ADC RDY0/1 bit in the ADCSTAT SFR to determine
the end of calibration by using a polling sequence or an interrupt
driven routine. If required, the NOEXREF0/1 bits can be moni-
tored to detect unconnected or low voltage errors in the reference
during conversion. In the event of the reference becoming
disconnected, causing a NOXREF flag during a calibration, the
calibration is immediately halted and no write to the calibration
SFRs takes place.
Internal Calibration Example
With chop enabled, a zero-scale or offset calibration should
never be required, although a full-scale or gain calibration may
be required. However, if a full internal calibration is required,
the procedure should be to select a PGA gain of 1 (±2.56 V) and
perform a zero-scale calibration (MD2...0 = 100B in the
ADCMODE register). Next, select and perform full-scale
calibration by setting MD2...0 = 101B in the ADCMODE SFR.
Now select the desired PGA range and perform a zero-scale
calibration again (MD2..0 = 100B in ADCMODE) at the new
PGA range. The reason for the double zero-scale calibration is
that the internal calibration procedure for full-scale calibration
automatically selects the reference in voltage at PGA = 1.
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