參數(shù)資料
型號： ADUC848BCPZ62-5
廠商： Analog Devices Inc
文件頁數(shù)： 81/108頁
文件大小： 0K
描述： IC MCU FLASH W/16BIT ADC 56LFCSP
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 74 of 108
P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can
act as an alternate PWM clock source. When selected as the
PWM outputs, they overwrite anything written to P2.5 or P2.6.
Table 47. Port 2 Alternate Functions
Pin No.
Alternate Function
P2.0
SCLOCK for SPI
P2.1
MOSI for SPI
P2.2
MISO for SPI
P2.3
SS and T2 clock input
P2.4
T2EX alternate control for T2
P2.5
PWM0 output
P2.6
PWM1 output
P2.7
PWMCLK
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DVDD
ADDR
P2.x
PIN
DVDD
INTERNAL
PULL-UP
Q
04741-069
Figure 50. Port 2 Bit Latch and I/O Buffer
Port 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR (B0H). Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and, in
that state, can be used as inputs. As inputs, Port 3 pins pulled
externally low source current because of the internal pull-ups.
Port 3 pins with 0s written to them drive a logic low output
voltage (VOL) and are capable of sinking 4 mA. Port 3 pins also
have various secondary functions as described in Table 48. The
alternate functions of Port 3 pins can be activated only if the
corresponding bit latch in the P3 SFR contains a 1. Otherwise,
the port pin remains at 0.
Table 48. Port 3 Alternate Functions
Pin No.
Alternate Function
P3.0
RxD (UART input pin, or serial data I/O in Mode 0)
P3.1
TxD (UART output pin, or serial clock output in Mode 0)
P3.2
INT0 (External Interrupt 0)
P3.3
INT1 (External Interrupt 1)
P3.4
T0 (Timer/Counter 0 external input)
P3.5
T1 (Timer/Counter 1 external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DVDD
P3.x
PIN
INTERNAL
PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Q
04741-071
Figure 51. Port 3 Bit Latch and I/O Buffer
Read-Modify-Write Instructions
Some 8051 instructions read the latch while others read the pin.
The instructions that read the latch rather than the pins are the
ones that read a value, possibly change it, and rewrite it to the
latch. These are called read-modify-write instructions, which
are listed in Table 49. When the destination operand is a port or
a port bit, these instructions read the latch rather than the pin.
Table 49. Read-Modify-Write Instructions
Instruction
Description
ANL
Logical AND, for example, ANL P1, A
ORL
Logical OR, for example, ORL P2, A
XRL
Logical EX-OR, for example, XRL P3, A
JBC
Jump if Bit = 1 and clear bit, for example, JBC
P1.1, LABEL
CPL
Complement bit, for example, CPL P3.0
INC
Increment, for example, INC P2
DEC
Decrement, for example, DEC P2
DJNZ
Decrement and jump if not zero, for example,
DJNZ P3, LABEL
MOV PX.Y, C1
Move Carry to Bit Y of Port X
CLR PX.Y1
Clear Bit Y of Port X
SETB PX.Y1
Set Bit Y of Port X
___________________________________________
1
These instructions read the port byte (all 8 bits), modify the addressed bit,
and write the new byte back to the latch.
Read-modify-write instructions are directed to the latch rather
than to the pin to avoid a possible misinterpretation of the
voltage level of a pin. For example, a port pin might be used to
drive the base of a transistor. When 1 is written to the bit, the
transistor is turned on. If the CPU reads the same port bit at the
pin rather than the latch, it reads the base voltage of the
transistor and interprets it as Logic 0. Reading the latch rather
than the pin returns the correct value of 1.
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