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| 型號： | ADUC848BCPZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH W/16BIT ADC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x16b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 26 of 108
ADC CIRCUIT INFORMATION
The ADuC845 incorporates two 10-channel (8-channel on the
MQFP package) 24-bit Σ- ADCs, while the ADuC847 and
ADuC848 each incorporate a single 10-channel (8-channel on
the MQFP package) 24-bit and 16-bit Σ- ADC.
Each part also includes an on-chip programmable gain
amplifier and configurable buffering (neither is available on the
auxiliary ADC on the ADuC845). The parts also incorporate
digital filtering intended for measuring wide dynamic range and
low frequency signals such as those in weigh-scale, strain-gage,
pressure transducer, or temperature measurement applications.
The ADuC845/ADuC847/ADuC848 can be configured as four
or five (MQFP/LFCSP package) fully-differential input channels
or as eight or ten (MQFP/LFCSP package) pseudo differential
input channels referenced to AINCOM. The ADC on each part
(primary only on the ADuC845) can be fully buffered internally,
and can be programmed for one of eight input ranges from
±20 mV to ±2.56 V (VREF × 1.024). Buffering the input channel
means that the part can handle significant source impedances
on the selected analog input and that RC filtering (for noise
rejection or RFI reduction) can be placed on the analog inputs.
If the ADC is used with internal buffering disabled
(ADC0CON1.7 = 1, ADC0CON1.6 = 0), these unbuffered
inputs provide a dynamic load to the driving source. Therefore,
resistor/capacitor combinations on the inputs can cause dc gain
errors, depending on the output impedance of the source that is
driving the ADC inputs.
Table 8 and Table 9 show the allowable external resistance/
capacitance values for unbuffered mode such that no gain error
at the 16-bit and 20-bit levels, respectively, is introduced. When
used with internal buffering enabled, it is recommended that a
capacitor (10 nF to 100 nF) be placed on the input to the ADC
(usually as part of an antialiasing filter) to aid in noise
performance.
The input channels are intended to convert signals directly from
sensors without the need for external signal conditioning. With
internal buffering disabled (relevant bits set/cleared in
ADC0CON1), external buffering might be required.
When the internal buffer is enabled, it might be necessary to
offset the negative input channel by +100 mV and to offset the
positive channel by 100 mV if the reference range is AVDD.
This accounts for the restricted common-mode input range in
the buffer. Some circuits, for example, bridge circuits, are
inherently suitable to use without having to offset where the
output voltage is balanced around VREF/2 and is not sufficiently
large to encroach on the supply rails. Internal buffering is not
available on the auxiliary ADC (ADuC845 only). The auxiliary
ADC (ADuC845 only) is fixed at a gain range of ±2.50 V.
The ADCs use a Σ-Δ conversion technique to realize up to
24 bits on the ADuC845 and the ADuC847, and up to 16 bits on
the ADuC848 of no missing codes performance (20 Hz update
rate, chop enabled). The Σ-Δ modulator converts the sampled
input signal into a digital pulse train whose duty cycle contains
the digital information. A sinc3 programmable low-pass filter
(see Table 28) is then used to decimate the modulator output
data stream to give a valid data conversion result at program-
mable output rates. The signal chain has two modes of operation,
chop enabled and chop disabled. The CHOP bit in the
ADCMODE register enables or disables the chopping scheme.
Table 8. Maximum Resistance for No 16-Bit Gain Error (Unbuffered Mode)
External Capacitance
Gain
0 pF
50 pF
100 pF
500 pF
1000 pF
5000 pF
1
111.3 k
27.8 k
16.7 k
4.5 k
2.58 k
700
2
53.7 k
13.5 k
8.1 k
2.2 k
1.26 k
360
4
25.4 k
6.4 k
3.9 k
1.0 k
600
170
8–128
10.7 k
2.9 k
1.7 k
480
270
75
Table 9. Maximum Resistance for No 20-Bit Gain Error (Unbuffered Mode)
External Capacitance
Gain
0 pF
50 pF
100 pF
500 pF
1000 pF
5000 pF
1
84.9 k
21.1 k
12.5 k
3.2 k
1.77 k
440
2
42.0 k
10.4 k
6.1 k
1.6 k
880
220
4
20.5 k
5.0 k
2.9 k
790
430
110
8–128
8.8 k
2.3 k
1.3 k
370
195
50
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