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參數(shù)資料
| 型號(hào)： | ADUC848BCPZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH W/16BIT ADC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x16b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 42 of 108
Notes on the ADCMODE Register
Any change to the MD bits immediately resets both ADCs
(auxiliary ADC only applicable to the ADuC845). A write
to the MD2–MD0 bits with no change in contents is also
treated as a reset. (See the exception to this in the third
note of this section.)
If ADC1CON1 and ADC1CON2 are written when
ADC0EN = 1, or if ADC0EN is changed from 0 to 1, both
ADCs are also immediately reset. In other words, the
primary ADC is given priority over the auxiliary ADC and
any change requested on the primary ADC is immediately
responded to. Only applicable to the ADuC845.
On the other hand, if ADC1CON is written to or if
ADC1EN is changed from 0 to 1, only the auxiliary ADC
is reset. For example, if the primary ADC is continuously
converting when the auxiliary ADC change or enable
occurs, the primary ADC continues undisturbed. Rather
than allow the auxiliary ADC to operate with a phase
difference from the primary ADC, the auxiliary ADC falls
into step with the outputs of the primary ADC. The result
is that the first conversion time for the auxiliary ADC is
delayed by up to three outputs while the auxiliary ADC
update rate is synchronized to the primary ADC. Only
applicable to ADuC845. If the ADC1CON write occurs
after the primary ADC has completed its operation, the
auxiliary ADC can respond immediately without having to
fall into step with the primary ADCs output cycle.
If the parts are powered down via the PD bit in the PCON
register, the current ADCMODE bits are preserved, that is,
they are not reset to default state. Upon a subsequent
resumption of normal operating mode, the ADCs restarts
the selected operation defined by the ADCMODE register.
Once ADCMODE has been written with a calibration
mode, the RDY0/1 (ADuC845 only) bits (ADCSTAT) are
reset and the calibration commences. On completion, the
appropriate calibration registers are written, the relevant
bits in ADCSTAT are written, and the MD2–MD0 bits are
reset to 000B to indicate that the ADC is back in power-
down mode.
Any calibration request of the auxiliary ADC while the
temperature sensor is selected fails to complete. Although
the RDY1 bit is set at the end of the calibration cycle, no
update of the calibration SFRs takes place, and the ERR1
bit is set. ADuC845 only.
Calibrations performed at maximum SF (see Table 28)
value (slowest ADC throughput rate) help to ensure
optimum calibration.
The duration of a calibration cycle is 2/Fadc for chop-on
mode and 4/Fadc for chop-off mode.
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