參數(shù)資料
型號： ADV7180WBCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 66/116頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER SDTV 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
Data Sheet
ADV7180
Rev. I | Page 53 of 116
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC END
PVENDSIGN
ODD FIELD?
0
1
NO
YES
PVENDDELO
VSEHO
ADDITIONAL
DELAY BY
1LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
05
70
0-
0
37
Figure 46. PAL VSYNC End
PVENDDELO, PAL VSYNC End Delay on Odd Field,
Address 0xE9[7]
When PVENDDELO is 0 (default), there is no delay.
Setting PVENDDELO to 1 delays VSYNC going low on an odd
field by a line relative to PVEND.
PVENDDELE, PAL VSYNC End Delay on Even Field,
Address 0xE9[6]
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays VSYNC going low on an even
field by a line relative to PVEND.
PVENDSIGN, PAL VSYNC End Sign, Address 0xE9[5]
Setting PVENDSIGN to 0 (default) delays the end of VSYNC
(set for user manual programming).
Setting PVENDSIGN to 1 advances the end of VSYNC (not
recommended for user programming).
PVEND[4:0], PAL VSYNC End, Address 0xE9[4:0]
The default value of PVEND is 10100, indicating the PAL
VSYNC end position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal on the VS pin are modified.
PFTOGDELO, PAL Field Toggle Delay on Odd Field,
Address 0xEA[7]
When PFTOGDELO is 0 (default), there is no delay.
Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.
PFTOGDELE, PAL Field Toggle Delay on Even Field,
Address 0xEA[6]
When PFTOGDELE is 0, there is no delay.
Setting PFTOGDELE to 1 (default) delays the F toggle/transition
on an even field by a line relative to PFTOG.
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA[5]
Setting PFTOGSIGN to 0 delays the field transition. Set for user
manual programming.
Setting PFTOGSIGN to 1 (default) advances the field transition
(not recommended for user programming).
PFTOG, PAL Field Toggle, Address 0xEA[4:0]
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
For all NTSC/PAL field timing controls, the F bit in the AV
code and the field signal on the FIELD pin are modified.
ADVANCE TOGGLE OF
FIELD BY PFTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
PFTOGSIGN
ODD FIELD?
0
1
NO
YES
PFTOGDELE
ADDITIONAL
DELAY BY
1LINE
1
0
PFTOGDELO
ADDITIONAL
DELAY BY
1LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
05
70
0-
0
38
Figure 47. PAL F Toggle
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參數(shù)描述
ADV7180WBST48Z 制造商:Analog Devices 功能描述:
ADV7180WBST48Z-RL 功能描述:視頻 IC 10-bit 4x Oversampling SDTV Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
ADV7180WBSTZ 功能描述:視頻 IC 10-bit 4x Oversampling SDTV Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
ADV7180WBSTZ-REEL 功能描述:視頻 IC 10-bit 4x Oversampling SDTV Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
ADV7181 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder
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