參數(shù)資料
型號(hào)： ADV7183A
廠(chǎng)商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder
中文描述： 標(biāo)清多格式視頻解碼器
文件頁(yè)數(shù)： 22/104頁(yè)
文件大小： 894K
代理商： ADV7183A
ADV7183A
SDP SYNC PROCESSING
The SDP extracts syncs embedded in the video data stream.
There is currently no support for external HS/VS inputs. The
sync extraction has been optimized to support imperfect video
sources (e.g., videocassette recorders with head switches). The
actual algorithm used employs a coarse detection based on a
threshold crossing followed by a more detailed detection using
an adaptive interpolation algorithm. The raw sync information
is sent to a line-length measurement and prediction block. The
output of this is then used to drive the digital resampling
section to ensure that the SDP outputs 720 active pixels per line.
Rev. A | Page 22 of 104
The sync processing on the ADV7183A also includes two
specialized postprocessing blocks that filter and condition the
raw sync information retrieved from the digitized analog video.
VSYNC Processor. This block provides extra filtering of the
detected VSYNCs to give improved vertical lock.
HSYNC Processor. The HSYNC processor is designed to
filter incoming HSYNCs that have been corrupted by
noise, providing much improved performance for video
signals with stable time base but poor SNR.
SDP VBI DATA RECOVERY
The SDP can retrieve the following information from the input
video:
Wide-screen signaling (WSS)
Copy generation management system (CGMS)
Closed caption (CC)
Macrovision protection presence
EDTV data
Gemstar compatible data slicing
The SDP is also capable of automatically detecting the incoming
video standard with respect to
Color subcarrier frequency
Field rate
Line rate
and can configure itself to support PAL-BGHID, PAL-M/N,
PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz,
NTSC4.43, and PAL60.
SDP GENERAL SETUP
Video Standard Selection (SDP)
The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal
circumstances, this should not be necessary. The VID_SEL[3:0]
bits default to an autodetection mode that supports PAL, NTSC,
SECAM, and variants thereof.
Refer to the Autodetection of SDP Modes section for more
information on the autodetection system.
Autodetection of SDP Modes
In order to guide the autodetect system of the SDP block,
individual enable bits are provided for each of the supported
video standards. Setting the relevant bit to 0 inhibits the
standard from being detected automatically. Instead, the system
picks the closest of the remaining enabled standards. The results
of SDP autodetection can be read back via the status registers.
See the Global Status Registers section for more information.
Table 30. VID_SEL Function
VID_SEL[3:0]
Address 0x00 [7:4]
0000*
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
*Default value.
Description
Autodetect (PAL BGHID) <–> NTSC J.
Autodetect (PAL BGHID) <–> NTSC M.
Autodetect (PAL N) <–> NTSC J.
Autodetect (PAL N) <–> NTSC M.
NTSC J (1)
NTSC M (1).
PAL 60.
NTSC 4.43 (1).
PAL BGHID.
PAL N ( = PAL BGHID (with pedestal)).
PAL M (without pedestal).
PAL M.
PAL combination N.
PAL combination N (with pedestal).
SECAM.
SECAM (with pedestal).
AD_SEC525_EN Enable Autodetection of SECAM 525 line
video (SDP), Address 0x07, [7]
Table 31. AD_SEC525_EN Function
AD_SEC525_EN
Description
0*
Disable the autodetection of a 525-line
system with a SECAM style, FM-modulated
color component.
1
Enable the detection.
*Default value.
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