參數(shù)資料
型號: ADV7183A
廠商: Analog Devices, Inc.
英文描述: Multiformat SDTV Video Decoder
中文描述: 標(biāo)清多格式視頻解碼器
文件頁數(shù): 50/104頁
文件大小: 894K
代理商: ADV7183A
ADV7183A
Rev. A | Page 50 of 104
0
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
VSYNC BEGIN
PVBEGSIGN
ODD FIELD
0
1
NO
YES
PVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 28. PAL VSync Begin
PVBEGDELO PAL VSync Begin Delay on Odd Field,
Address 0xE8, [7]
Table 124. PVBEGDELO Function
PVBEGDELO
Description
0*
No delay.
1
Delay VSync going high on an odd field by a line
relative to PVBEG.
*Default value.
PVBEGDELE PAL VSync Begin Delay on Even Field,
Address 0xE8, [6]
Table 125. PVBEGDELE Function
PVBEGDELE
Description
0
No delay.
1*
Delay VSync going high on an even field by a line
relative to PVBEG.
*Default value.
PVBEGSIGN PAL VSync Begin Sign, Address 0xE8, [5]
Table 126. PVBEGSIGN Function
PVBEGSIGN
Description
0
Delay begin of VSync. Set for user manual
programming.
1*
Advance begin of VSync. Not recommended for
user programming.
*Default value.
PVBEG[4:0] PAL VSync Begin, Address 0xE8, [4:0]
Table 127. PVBEG Function
PVBEG
Description
00101*
PAL VSync begin position.
*Default value.
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
0
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC END
PVENDSIGN
ODD FIELD
0
1
NO
YES
PVENDDELO
VSEHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 29. PAL VSync End
PVENDDELO PAL VSync End Delay on Odd Field,
Address 0xE9,[7]
Table 128. PVENDDELO Function
PVENDDELO
Description
0*
No delay.
1
Delay VSync going low on an odd field by a line
relative to PVEND.
*Default value.
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