參數(shù)資料
型號: ADZS-BF537-ASKIT
廠商: Analog Devices Inc
文件頁數(shù): 24/68頁
文件大小: 0K
描述: BOARD EVAL SKIT ADSP-BF537
產(chǎn)品培訓模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝: 1
系列: Blackfin®
類型: DSP:音頻
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品:
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 30 of 68
|
February 2014
TIMING SPECIFICATIONS
Component specifications are subject to change
without notice.
Clock and Reset Timing
Table 22. Clock Input and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 14. Since
by default the PLL is multiplying the CLKIN frequency by 10 MHz, 300 MHz, and 400 MHz speed grade parts can not use the full CLKIN period range.
2 Applies to PLL bypass mode and PLL non bypass mode.
3 CLKIN frequency must not change on the fly.
4 If the DF bit in the PLL_CTL register is set, then the maximum t
CKIN period is 50 ns.
20.0
100.0
ns
tCKINL
CLKIN Low Pulse
8.0
ns
tCKINH
CLKIN High Pulse
8.0
ns
tBUFDLAY
CLKIN to CLKBUF Delay
10
ns
tWRST
RESET Asserted Pulse Width Low
11 × tCKIN
ns
tNOBOOT
RESET Deassertion to First External Access Delay5
5 Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
3 × tCKIN
5 × tCKIN
ns
Figure 9. Clock and Reset Timing
Table 23. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR
RESET Deasserted After the VDDINT, VDDEXT, VDDRTC, and CLKIN Pins Are Stable and
Within Specification
3500 × tCKIN
ns
In Figure 10, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC
Figure 10. Power-Up Reset Timing
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
tBUFDLAY
RESET
CLKBUF
RESET
tRST_IN_PWR
CLKIN
V
DD_SUPPLIES
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