參數(shù)資料
型號(hào): ADZS-BF537-ASKIT
廠商: Analog Devices Inc
文件頁數(shù): 27/68頁
文件大小: 0K
描述: BOARD EVAL SKIT ADSP-BF537
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: DSP:音頻
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品:
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 33 of 68
|
February 2014
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 13 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
Parameter1, 2
Min
Max
Unit
Timing Requirements
tBS
BR Asserted to CLKOUT Low Setup
4.6
ns
tBH
CLKOUT Low to BR Deasserted Hold Time
0.0
ns
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
4.5
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
4.5
ns
tDBG
CLKOUT High to BG Asserted Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH Asserted Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
1 These timing parameters are based on worst-case operating conditions.
2 The pad loads for these timing parameters are 20 pF.
Figure 13. External Port Bus Request and Grant Cycle Timing
AMSx
CLKOUT
BG
BGH
BR
ADDR 19-1
ABE1-0
tBH
tBS
tSD
tSE
tSD
tSE
t
EBG
tDBG
t
EBH
tDBH
AWE
ARE
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