參數(shù)資料
型號(hào): ADZS-BF537-ASKIT
廠商: Analog Devices Inc
文件頁數(shù): 30/68頁
文件大小: 0K
描述: BOARD EVAL SKIT ADSP-BF537
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: DSP:音頻
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品:
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 36 of 68
|
February 2014
Parallel Peripheral Interface Timing
Figure 23 on Page 41 describe parallel peripheral interface
operations.
Table 29. Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
PPI_CLK Width1
6.0
ns
tPCLK
PPI_CLK Period1
15.0
ns
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
6.7
ns
tHFSPE
External Frame Sync Hold After PPI_CLK
1.0
ns
tSDRPE
Receive Data Setup Before PPI_CLK
3.5
ns
tHDRPE
Receive Data Hold After PPI_CLK
1.5
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
8.0
ns
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
1.7
ns
tDDTPE
Transmit Data Delay After PPI_CLK
8.0
ns
tHDTPE
Transmit Data Hold After PPI_CLK
1.8
ns
1 PPI_CLK frequency cannot exceed fSCLK/2.
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
tHDRPE
tSDRPE
tHOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tDFSPE
tPCLK
tPCLKW
tPCLK
tSFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tHFSPE
tHDRPE
tSDRPE
tPCLKW
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