參數(shù)資料
型號(hào): ADZS-BF537-ASKIT
廠商: Analog Devices Inc
文件頁(yè)數(shù): 35/68頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL SKIT ADSP-BF537
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: DSP:音頻
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品:
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 40 of 68
|
February 2014
Table 32. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx
1
0ns
tDDTTE
Data Disable Delay from External TSCLKx1, 2
10.0
ns
tDTENI
Data Enable Delay from Internal TSCLKx1
–2.0
ns
tDDTTI
Data Disable Delay from Internal TSCLKx1, 2
3.0
ns
1 Referenced to drive edge.
2 Applicable to multichannel mode only. TSCLKx is tied to RSCLKx.
Figure 22. Enable and Three-State
TSCLKx
DTx
DRIVE EDGE
tDDTTE/I
tDTENE/I
DRIVE EDGE
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