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參數(shù)資料
| 型號： | AGLE600V5-FG484C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 30/156頁 |
| 文件大?。?/td> | 5023K |
| 代理商： | AGLE600V5-FG484C |
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IGLOOe DC and Switching Characteristics
Ad vance v0.3
2- 111
Part Number and Revision Date
Part Number 51700096-002-2
Revised July 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (Advance v0.3)
Page
Advance v0.2
(June 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of
core voltage support. The document was updated to change 1.2 V / 1.5 V to
1.2 V to 1.5 V.
Advance v0.1
(January 2008)
Tables have been updated to reflect default values in the software. The
default I/O capacitance is 5 pF. Tables have been updated to include the
LVCMOS 1.2 V I/O set.
DDR Tables have two additional data points added to reflect both edges for
Input DDR setup and hold time.
The power data table has been updated to match SmartPower data rather
then simulation values.
N/A
Table 2-1 Absolute Maximum Ratings was updated to add VMV to the VCCI
parameter row and remove the word "output" from the parameter
description for VCCI. Table note 3 was added.
Table 2-2 Recommended Operating Conditions 4 was updated to include the
TJ parameter. Table note 9 is new.
Temperature1, the maximum operating junction temperature was changed
from 110° to 100°.
VMV was removed fromTable 2-4 Overshoot and Undershoot Limits 1. The
title of the table was revised to remove "as measured on quiet I/Os." Table
note 2 was revised to remove "estimated SSO density over cycles." Table note
3 was deleted.
The "PLL Behavior at Brownout Condition" section is new.
is new.
EQ 2-2 was updated. The temperature was changed to 100°C, and therefore
the end result changed.
The table notes for Table 2-8 Quiescent Supply Current (IDD), IGLOOe
Shutdown Mode (VCC, VCCI = 0 V)* were updated to remove VMV and include
PDC6 and PDC7. VCCI and VJTAG were removed from the statement about IDD in
the table note for Table 2-9 Quiescent Supply Current (IDD), IGLOOe Sleep
and PDC7.
Table note 3 was added to Table 2-12 Summary of I/O Input Buffer Power
(per pin) – Default I/O Software Settings and referenced for 1.2 V LVCMOS.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLE600V5-FGG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V5-FGG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| ACBQ20TTEB270K/390M | RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.000039uF, SURFACE MOUNT, 20 |
| ACBQ20TTEB270K/401M | RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.0004uF, SURFACE MOUNT, 20 |
| ACBQ20TTEB270K/430M | RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.000043uF, SURFACE MOUNT, 20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLE600V5-FG484I | 功能描述:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AGLE600V5-FG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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