參數(shù)資料
型號: AGLE600V5-FG484C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù): 81/156頁
文件大小: 5023K
代理商: AGLE600V5-FG484C
IGLOOe DC and Switching Characteristics
2- 16
Advance v0.3
User I/O Characteristics
Timing Model
Figure 2-3 Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL
LVDS,
BLVDS,
M-LVDS
GTL+ 3.3V
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL/LVCMOS 3.3 V
Output drive strength = 24 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS 3.3 V
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL/LVCMOS 3.3 V
Clock
Input LVTTL/LVCMOS 3.3 V
Clock
Input LVTTL/LVCMOS 3.3 V
Clock
t
PD = 1.19 ns
t
PD = 1.04 ns
t
DP = 1.75 ns
t
PD = 1.77 ns
t
DP = 3.13 ns
t
PD = 1.33 ns
t
PD = 0.85 ns
t
DP = 2.76 ns
t
DP = 3.30 ns
t
OCLKQ = 1.02 ns
t
DP = 1.85 ns
t
OSUD = 0.52 ns
t
PY = 1.10 ns
t
CLKQ = 0.90 ns
t
SUD = 0.82 ns
t
PY = 1.10 ns
t
PD = 0.90 ns
t
CLKQ = 0.90 ns
t
SUD = 0.82 ns
t
PY = 1.62 ns
t
PY = 1.10 ns
t
ICLKQ = 0.43 ns
t
ISUD = 0.47 ns
t
PY = 1.45 ns
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