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參數(shù)資料
| 型號： | AGLE600V5-FG484C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 31/156頁 |
| 文件大小： | 5023K |
| 代理商： | AGLE600V5-FG484C |
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IGLOOe DC and Switching Characteristics
2- 112
Advance v0.3
Advance v0.1
(continued)
updated to reflect that power was measured on VCCI. Table note 4 is new.
updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank
quiescent power.
A
table
subtitle
was
added
for
The "Total Static Power Consumption—PSTAT" section was updated to revise
the calculation of PSTAT, including PDC6 and PDC7.
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to PPLL
= PDC4 + PAC13 * FCLKOUT.
The "Timing Model" was updated to be consistent with the revised timing
numbers.
changed to TA in notes 1 and 2.
Table 2-31 Schmitt Trigger Input Hysteresis was updated to included a
hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
N/A
The "1.2 V LVCMOS (JESD8-12A)" section is new.
Advance v0.4
(December 2007)
This document was previously in datasheet Advance v0.4. As a result of
moving to the handbook format, Actel has restarted the version numbers. The
new version number is Advance v0.1.
N/A
Advance v0.3
(September 2007)
Table 2-4 IGLOOe CCC/PLL Specification and Table 2-5 IGLOOe CCC/PLL
Specification were updated.
2-18,
2-19
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core
.
2-60
Figure 2-38 Flash*Freeze Mode Type 1 – Timing Diagram was updated to
modify the LSICC signal.
2-56
Table 2-32 Flash*Freeze Pin Location in IGLOOe Family Packages (device-
independent) was updated for the FG896 package.
2-64
Figure 2-40 Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
2-58
Information regarding calculation of the quiescent supply current was added
to the "Quiescent Supply Current" section.
3-6
Table 3-8 Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode was
updated.
3-6
Table 3-9 Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)
was updated.
3-6
Table 3-11 Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was
updated.
3-6
Previous Version
Changes in Current Version (Advance v0.3)
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLE600V5-FGG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V5-FGG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| ACBQ20TTEB270K/390M | RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.000039uF, SURFACE MOUNT, 20 |
| ACBQ20TTEB270K/401M | RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.0004uF, SURFACE MOUNT, 20 |
| ACBQ20TTEB270K/430M | RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.000043uF, SURFACE MOUNT, 20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLE600V5-FG484I | 功能描述:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AGLE600V5-FG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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