參數(shù)資料
型號： AGLE600V5-FG484C
元件分類： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù)： 87/156頁
文件大?。?/td> 5023K
代理商： AGLE600V5-FG484C
IGLOOe DC and Switching Characteristics
2- 22
Advance v0.3
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-22 Summary of AC Measuring Points
Standard
Input Reference
Voltage (VREF_TYP)
Board Termination
Voltage (VTT_REF)
Measuring Trip
Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS
–
1.4 V
2.5 V LVCMOS
–
1.2 V
1.8 V LVCMOS
–
0.90 V
1.5 V LVCMOS
–
0.75 V
1.2 V LVCMOS
–
0.6 V
3.3 V PCI
–
0.285*VCCI (RR)
–
0.615*VCCI (FF))
3.3 V PCI-X
–
0.285*VCCI (RR)
–
0.615*VCCI (FF)
3.3 V GTL
0.8 V
1.2 V
VREF
2.5 V GTL
0.8 V
1.2 V
VREF
3.3 V GTL+
1.0 V
1.5 V
VREF
2.5 V GTL+
1.0 V
1.5 V
VREF
HSTL (I)
0.75 V
VREF
HSTL (II)
0.75 V
VREF
SSTL2 (I)
1.25 V
VREF
SSTL2 (II)
1.25 V
VREF
SSTL3 (I)
1.5 V
1.485 V
VREF
SSTL3 (II)
1.5 V
1.485 V
VREF
LVDS
–
Cross point
LVPECL
–
Cross point
Table 2-23 I/O AC Parameter Definitions
Parameter
Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
tDOUT
Data to Output Buffer delay through the I/O interface
tEOUT
Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN
Input Buffer to Data delay through the I/O interface
tPYS
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
tHZ
Enable to Pad delay through the Output Buffer—HIGH to Z
tZH
Enable to Pad delay through the Output Buffer—Z to HIGH
tLZ
Enable to Pad delay through the Output Buffer—LOW to Z
tZL
Enable to Pad delay through the Output Buffer—Z to LOW
tZHS
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
相關PDF資料
PDF描述
AGLE600V5-FGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
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相關代理商/技術參數(shù)
參數(shù)描述
AGLE600V5-FG484I 功能描述:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
AGLE600V5-FG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
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