參數(shù)資料
型號: AGLN125V5-FCSG81
元件分類: FPGA
英文描述: FPGA, PBGA81
封裝: 5 X 5 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-81
文件頁數(shù): 56/114頁
文件大?。?/td> 3991K
代理商: AGLN125V5-FCSG81
IGLOO nano DC and Switching Characteristics
2- 32
Advance v0.2
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-46 Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
1 I
IH
2
Drive
Strength Min., V
Max., V
Min., V
Max., V Max., V
Min., V
mA mA Max., mA3 Max., mA3 A4 A4
2 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
9
11
10
4 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
17
22
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.
Input current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-9 AC Loading
Table 2-47 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
01.8
0.9
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
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