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參數(shù)資料
| 型號(hào)： | AK4122 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 BIT 96KHZ SRC WITH DIR |
| 中文描述： | 24位96kHz Src與迪爾 |
| 文件頁(yè)數(shù)： | 17/54頁(yè) |
| 文件大?。?/td> | 403K |
| 代理商： | AK4122 |
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ASAHI KASEI
[AK4122]
MS0267-E-03
2004/08
- 17 -
Note 1. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately
by Table 2.
M/S2 pin
Mode
Unused pin
Pin I/O
MCLK2
I
BICK2
I
LRCK2
I
SDTIO
I
MCLK2
I
BICK2
O
LRCK2
O
SDTIO
I
Table 2. Pin Setting for PORT2
Note 2. In this case, PORT3 is output port. If PORT3 is unused, the digital I/O pins should be processed appropriately
by Table 3.
M/S3 pin
Mode
Unused pin
Pin I/O
OMCLK
I
BICK
I
LRCK
I
SDTO
O
OMCLK
I
BICK
O
LRCK
O
SDTO
O
Table 3. Pin Setting for PORT3
System Clock
PORT1 can be operated in slave mode only. PORT2 and PORT3 work in master mode and slave mode. Internal system
clock is created by internal PLL using LRCK1, LRCK2 or LRCK of DIR. The MCLK is not needed when PORT2 and
PORT3 are in slave mode and then please set MCLK2 pin and OMCLK pin to DVSS. However, when PORT2 and
PORT3 are used in master mode, MCLK2 pin and OMCLK pin should be supplied to MCLK. The M/S2 pin and M/S3
pin select between master and slave mode. Table 4 and 5 show setting of MCLK frequency that PORT2 and PORT3 are
master mode. In case of detecting the sampling frequency by MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of
selected output port (PORT2 or PORT3) should be input.
Setting
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be open.
This pin should be open.
This pin should be connected to DVSS.
L
Slave
H
Master
Setting
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be open.
This pin should be connected to DVSS.
This pin should be open.
This pin should be open.
This pin should be open.
L
Slave
H
Master
MCLK2
ICKS1
ICKS0
32kHz
≤
fs
≤
48kHz
256fs
384fs
512fs
768fs
Table 4. MCLK2 frequency select for Master mode
48kHz
<
fs
≤
96kHz
256fs
384fs
N/A
N/A
0
0
1
1
0
1
0
1
Default
OMCLK
OCKS1
OCKS0
32kHz
≤
fs
≤
48kHz
256fs
384fs
512fs
768fs
Table 5. OMCLK frequency select for Master mode
48kHz
<
fs
≤
96kHz
256fs
384fs
N/A
N/A
0
0
1
1
0
1
0
1
Default
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4122_1 | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
| AK4122A | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
| AK4122AVQ | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
| AK4122AVQP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:SRC + DIR |
| AK4122VQ | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
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