- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄253907 > AM29F017D-120FD (SPANSION LLC) 2M X 8 FLASH 5V PROM, 120 ns, PDSO48 PDF資料下載
參數(shù)資料
| 型號： | AM29F017D-120FD |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 2M X 8 FLASH 5V PROM, 120 ns, PDSO48 |
| 封裝： | MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 11/46頁 |
| 文件大小： | 1387K |
| 代理商： | AM29F017D-120FD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
July 29, 2005
Am29F017D
17
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV004T-70RFF | 512K X 8 FLASH 3V PROM, 70 ns, PDSO40 |
| AM29LV004T-80EF | 512K X 8 FLASH 3V PROM, 80 ns, PDSO40 |
| AT28C1024-20BM/883 | 64K X 16 EEPROM 5V, 200 ns, CDIP40 |
| AM99C641-45/LMC | 64K X 1 STANDARD SRAM, 45 ns, CQCC22 |
| AM27128A-15LIB | 16K X 8 UVPROM, 150 ns, CQCC32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F017D-70FI | 制造商:Spansion 功能描述:FLASH PARALLEL 5V 16MBIT 2MX8 70NS 48TSOP - Trays |
| am29f017d-90fc/t | 制造商:Advanced Micro Devices 功能描述: |
| AM29F032B-120ED | 制造商:Spansion 功能描述: |
| AM29F032B75ED | 制造商:Advanced Micro Devices 功能描述: |
| AM29F032B-75EF | 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:32M (4M X 8-BIT) 5V FLSH SCTR 制造商:Spansion 功能描述:IC, FLASH MEM, 32MBIT, 75NS, 40-TSOP, Memory Type:Flash - NOR, Memory Size:32Mbi |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。