![](http://datasheet.mmic.net.cn/160000/AM29F017D-120F4C_datasheet_8418637/AM29F017D-120F4C_15.png)
July 29, 2005
Am29F017D
13
pr e v i ous ly
pr ote c te d
sec t or
g r oup s
ar e
protected again.
Figure 1 shows the algorithm, and
the Temporary Sector/Sector Group Unprotect dia-
gram shows the timing waveforms, for this feature.
Figure 1.
Temporary Sector Group Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector Group
Unprotect
Completed (Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.