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| 型號： | Am29PDS322DB10 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory |
| 中文描述： | 32兆位（2米× 16位），1.8伏的CMOS只（1.8伏至2.2 V）同步讀/寫頁模式引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 2/50頁 |
| 文件大小： | 839K |
| 代理商： | AM29PDS322DB10 |
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ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
23569
Issue Date:
August 7, 2002
Rev:
A
Amendment/
+4
Am29PDS322D
32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V)
Simultaneous Read/Write Page-Mode Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
I
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
— Zero latency between read and write operations
I
Page Mode Operation
— 4 word page allows fast asynchronous reads
I
Dual Bank architecture
— One 4 Mbit bank and one 28 Mbit bank
I
SecSi (Secured Silicon) Sector: Extra 64 KByte
sector
—
Factory locked and identifiable:
16 byte Electronic
Serial Number available for factory secure, random
ID; verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
I
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
I
Package options
— 48-ball FBGA
I
Top or bottom boot block
I
Manufactured on 0.23 μm process technology
I
Compatible with JEDEC standards
—
Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
I
High performance
—
Access time as fast 40 ns (100 ns random access
time) at 1.8 V to 2.2 V V
CC
—
Random access time of 100 ns at 1.8 V to 2.2 V V
CC
will be required as customers migrate downward in
voltage
I
Ultra low power consumption (typical values)
—
2.5 mA active read current at 1 MHz for initial page
read
—
24 mA active read current at 10 MHz for initial page
read
—
0.5 mA active read current at 10 MHz for intra-page
read
—
1 mA active read current at 20 MHz for intra-page
read
—
200 nA in standby or automatic sleep mode
I
Minimum 1 million write cycles guaranteed per
sector
I
20 year data retention at 125
°
C
—
Reliable operation for the life of the system
SOFTWARE FEATURES
I
Data Management Software (DMS)
—
AMD-supplied software manages data programming,
enabling EEPROM emulation
—
Eases historical sector erase flash limitations
I
Erase Suspend/Erase Resume
—
Suspends erase operations to allow programming in
same bank
I
Data# Polling and Toggle Bits
—
Provides a software method of detecting the status of
program or erase cycles
I
Unlock Bypass Program command
—
Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
I
Any combination of sectors can be erased
I
Ready/Busy# output (RY/BY#)
—
Hardware method for detecting program or erase
cycle completion
I
Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state
machine to the read mode
I
WP#/ACC input pin
—
Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
—
Acceleration (ACC) function accelerates program
timing
—
ACC voltage is 8.5 V to 12.5 V
I
Sector protection
—
Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
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