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參數(shù)資料
| 型號： | Am29PDS322DT12 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory |
| 中文描述： | 32兆位（2米× 16位），1.8伏的CMOS只（1.8伏至2.2 V）同步讀/寫頁模式引導扇區(qū)閃存 |
| 文件頁數(shù)： | 11/50頁 |
| 文件大?。?/td> | 839K |
| 代理商： | AM29PDS322DT12 |
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10
Am29PDS322D
August 7, 2002
A D V A N C E I N F O R M A T I O N
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Automatic sleep mode current is drawn when CE# =
V
SS
± 0.3 V and
all inputs
are held at V
CC
± 0.3 V. If
CE# and RESET# voltages are not held within these
tolerances, the automatic sleep mode current will be
greater.
I
CC5
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
± 0.3 V, the de-
vice draws CMOS standby current (I
CC3
). If RESET# is
held at V
IL
but not within V
SS
± 0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a
“
0
”
(busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is
“
1
”
), the reset operation is com-
pleted within a time of t
READY
(not during Embedded
Algorithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
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