參數(shù)資料
型號： AM41LV3204MT10IT
廠商： ADVANCED MICRO DEVICES INC
元件分類： 存儲器
英文描述： Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA69
封裝： 8 X 10 MM, 1.20 MM HEIGHT, FBGA-69
文件頁數(shù)： 4/67頁
文件大?。?/td> 484K
代理商： AM41LV3204MT10IT
June 10, 2003
Am41LV3204M
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH,
SRAM Word Mode, CIOs = V
IL
......................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAM Word Mode, CIOs = V
CC
.....................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
SS
..................................................................13
Requirements for Reading Array Data ...................................14
Page Mode Read ....................................................................14
Writing Commands/Command Sequences ............................14
Write Buffer .............................................................................14
Accelerated ProgramOperation .............................................14
Autoselect Functions ..............................................................14
Automatic Sleep Mode ...........................................................15
RESET#: Hardware Reset Pin ...............................................15
Output Disable Mode ..............................................................15
................................................................................................16
Sector Group Protection and Unprotection .............................18
Table 6. Am29LV320MT Top Boot SectorProtection .....................18
................................................................................................18
Table 7. Am29LV320MB BottomBoot SectorProtection ................18
Write Protect (WP#) ................................................................18
Temporary Sector Group Unprotect .......................................19
Figure 1. Temporary Sector Group UnprotectOperation................ 19
Figure 2. In-SystemSector Group Protect/UnprotectAlgorithms... 20
SecSi (Secured Silicon) Sector Flash MemoryRegion ..........21
Table 8. SecSi Sector Contents ......................................................21
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection ......................................................22
Low VCC Write Inhibit ............................................................22
Write Pulse “Glitch” Protection ...............................................22
Logical Inhibit ..........................................................................22
Power-Up Write Inhibit ............................................................22
Common Flash Memory Interface (CFI). . . . . . . 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................25
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector CommandSequence ..26
Word ProgramCommand Sequence .....................................26
Unlock Bypass Command Sequence .....................................27
Write Buffer Programmng ......................................................27
Accelerated Program..............................................................28
Figure 4. Write Buffer Programmng Operation............................... 29
Figure 5. ProgramOperation.......................................................... 30
ProgramSuspend/ProgramResume Command Sequence ...30
Figure 6. ProgramSuspend/ProgramResume............................... 31
Chip Erase Command Sequence ...........................................31
Sector Erase Command Sequence ........................................31
Figure 7. Erase Operation............................................................... 32
Erase Suspend/Erase Resume Commands ...........................32
Write Operation Status . . . . . . . . . . . . . . . . . . . . 35
DQ7: Data#Polling .................................................................35
Figure 8. Data#Polling Algorithm.................................................. 35
DQ6: Toggle Bit I ....................................................................36
Figure 9. Toggle Bit Algorithm....................................................... 37
DQ2: Toggle Bit II ...................................................................37
Reading Toggle Bits DQ6/DQ2 ...............................................37
DQ5: Exceeded Timng Limts ................................................38
DQ3: Sector Erase Timer .......................................................38
DQ1: Write-to-Buffer Abort .....................................................38
Table 15. Write Operation Status ...................................................38
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 39
Figure 10. MaximumNegative OvershootWaveform................... 39
Figure 11. MaximumPositive OvershootWaveform..................... 39
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
SRAM DC and Operating Characteristics. . . . . . 41
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. Test Setup.................................................................... 42
Table 16. Test Specifications .........................................................42
Key to Switching Waveforms. . . . . . . . . . . . . . . . 42
Figure 13. Input Waveforms and Measurement Levels................. 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
Flash Read-Only Operations .................................................43
Figure 14. Read Operation Timngs............................................... 43
Figure 15. Page Read Timngs...................................................... 44
Hardware Reset (RESET#) ....................................................45
Figure 16. Reset Timngs............................................................... 45
Flash Erase and ProgramOperations ....................................46
Figure 17. ProgramOperation Timngs.......................................... 47
Figure 18. Accelerated ProgramTimng Diagram.......................... 47
Figure 19. Chip/Sector Erase Operation Timngs.......................... 48
Figure 20. Data# Polling Timngs (During Embedded Algorithms). 49
Figure 21. Toggle Bit Timngs (During Embedded Algorithms)...... 50
Figure 22. DQ2 vs. DQ6................................................................. 50
Temporary Sector Unprotect ..................................................51
Figure 23. Temporary Sector Group Unprotect TimngDiagram... 51
Figure 24. Sector Group Protect and Unprotect TimngDiagram.. 52
Alternate CE#Controlled Erase and ProgramOperations .....53
Figure 25. Alternate CE#Controlled Write (Erase/Program)
OperationTimngs.......................................................................... 54
SRAM Read Cycle ..................................................................55
Figure 26. SRAM Read Cycle—Address Controlled...................... 55
Figure 27. SRAM Read Cycle........................................................ 56
SRAMWrite Cycle ..................................................................57
Figure 28. SRAM Write Cycle—WE#Control................................ 57
Figure 29. SRAM Write Cycle—CE1#s Control............................. 58
Figure 30. SRAM Write Cycle—UB#s and LB#s Control............... 59
Erase And Programming Performance. . . . . . . . 60
Flash Latchup Characteristics. . . . . . . . . . . . . . . 60
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 61
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SRAM Data Retention. . . . . . . . . . . . . . . . . . . . . . 62
Figure 31. CE#1 Controlled Data Retention Mode......................... 62
Figure 32. CE2s Controlled Data Retention Mode......................... 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA)
8x10mmPackage ................................................................64
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 65
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