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參數(shù)資料
| 型號： | AM41LV3204MT10IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA69 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, FBGA-69 |
| 文件頁數(shù)： | 56/67頁 |
| 文件大?。?/td> | 484K |
| 代理商： | AM41LV3204MT10IT |
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June 10, 2003
Am41LV3204M
55
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Read Cycle
Figure 26.
SRAM Read Cycle—Address Controlled
Note:
CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
Parameter
Symbol
Description
Speed Option
Unit
10
t
RC
Read Cycle Time
Min
70
ns
t
AA
Address Access Time
Max
70
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
70
ns
t
OE
Output Enable Access Time
Max
35
ns
t
BA
LB#s, UB#s to Access Time
Max
70
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
Min
10
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
25
ns
t
OHZ
Output Disable to High-Z Output
Max
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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| AM41PDS3224DT110IT | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM |
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| AM41PDS3224DB10IT | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM |
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| AM41LV320MT10IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM |
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