參數(shù)資料
型號(hào)： AM42BDS640AGBC8IS
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 8 X 11.60 MM, FBGA-93
文件頁(yè)數(shù)： 5/72頁(yè)
文件大?。?/td> 1064K
代理商： AM42BDS640AGBC8IS
12
Am42BDS640AG
November 1, 2002
P R E L I M INARY
Table 1.
Device Bus Operations
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
= Active edge of CLK,
= Pulse Low,
= Rising edge of Pulse Low
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
2.
Do not apply CE#f = V
IL, CE1#s = VIL and CE2s = VIH at the same
time.
3.
Either CE1#s = V
IH or CE2s = VIL will disable the SRAM. If one of
these conditions is true, the other CE input is don’t care.
4.
X = Don’t care or open LB#s or UB#s.
5.
Default edge of CLK is the rising edge.
6.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector
7.
If ACC = V
HH, all sectors will be protected.
8.
If WP# = VIL, sectors 0,1 (bottom boot) or sectors 132, 133 (top
boot) are protected. If WP# = V
IH, the protection applied to the
aforementioned sectors depends on whether they were last
protected or unprotected using the method described in
Lock/Unlock Command Sequence”. Note that WP# must not be left
floating or unconnected.
Operation
CE#f
CE1#s
CE2s
OE#
WE#
A
[21–0]
DQ
[15–8]
DQ
[7–0]
LB#s
UB#s
RESET#
CLK
AVD#
Asynchronous Read from Flash,
Addresses Latched
LH
L
H
A
IN
I/O
X
H
X
Asynchronous Read from Flash,
Addresses Steady State
LH
L
H
A
IN
I/O
X
H
X
L
Asynchronous Write to Flash
L
H
L
H
L
A
IN
I/O
X
H
X
L
Synchronous Write to Flash
L
H
L
H
L
A
IN
I/O
X
H
X
CE# Standby
H
L
X
Hi-Z
X
H
X
Output Disable
L
HL
H
Hi-Z
LX
HX
X
HL
X
L
Hardware Reset
X
H
L
X
Hi-Z
X
L
X
Read from SRAM
H
L
H
L
H
A
IN
D
OUT
D
OUT
LL
HX
X
D
OUT
Hi-Z
H
L
Hi-Z
D
OUT
LH
Wirte to SRAM
H
L
H
X
L
A
IN
D
IN
D
IN
LL
HX
X
D
IN
Hi-Z
H
L
HI-Z
D
IN
LH
Flash Burst Read Operations
Load Starting Burst Address
L
H
L
X
H
Addr In
X
H
Advance Burst to next address with
appropriate Data presented on the
Data Bus
LH
L
H
HIGH
Z
Burst
Data Out
XX
H
Terminate current Burst read cycle
H
L
X
H
Hi-Z
X
H
X
Terminate current Burst read cycle
via RESET#
XH
L
X
H
Hi-Z
X
L
X
Terminate current Burst read cycle
and start new Burst read cycle
L
H
L
X
H
Hi-Z
I/O
X
H
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