參數(shù)資料
型號(hào)： AM50DL128BG
英文描述： Am50DL128BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： Am50DL128BG -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 4/70頁(yè)
文件大?。?/td> 1042K
代理商： AM50DL128BG
May 19, 2003
Am50DL9608G
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions ....................................7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
MCP Device Bus Operations . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations—Flash Word Mode .................... 10
Flash Device Bus Operations . . . . . . . . . . . . . . .11
Requirements for Reading Array Data ...................................11
Writing Commands/Command Sequences ............................11
Simultaneous Read/Write Operations with Zero Latency .......11
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................12
Table 2. Am29DL640G Sector Architecture ....................................13
Table 3. Am29DL640G Bank Address ............................................16
Table 4. Am29DL640G SecSi
Sector Addresses .......................16
Table 5. Am29DL320G Top Boot Sector Addresses .....................17
Table 6. Am29DL320G Top Boot SecSi
TM
Sector Addresses........ 18
Table 7. Am29DL320G BottomBoot Sector Addresses .................19
Table 8. Am29DL320G BottomBoot SecSi
TM
Sector Addresses... 20
Table 9. Am29DL640G Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................21
Table 10. Am29DL320G Top Boot Sector/Sector
Block Addresses forProtection/Unprotection ..................................22
Table 11. Am29DL320G BottomBoot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................22
Write Protect (WP#) ................................................................23
Table 12. WP#/ACC Modes ............................................................23
Temporary Sector Unprotect ..................................................23
Figure 1. Temporary Sector Unprotect Operation........................... 24
Figure 2. In-SystemSector Protect/Unprotect Algorithms.............. 25
SecSi (Secured Silicon) Sector
SectorFlashMemoryRegion .................................................26
Table 13. SecSi Sector Programmng ................................................26
Figure 3. SecSi Sector Protect Verify.............................................. 27
Hardware Data Protection ......................................................27
Common Flash Memory Interface (CFI) . . . . . . .27
Table 14. Am29DL640G CFI Query Identification String................ 28
Table 15. Am29DL640G SystemInterface String........................... 28
Table 16. Am29DL640G Device Geometry Definition..................... 29
Table 17. Am29DL640G Primary Vendor-Specific
Extended Query.............................................................................. 30
Table 18. Am29DL320G CFI Query Identification String................ 31
Table 19. Am29DL320G SystemInterface String........................... 31
Table 20. Am29DL320G Device Geometry Definition..................... 32
Table 21. Am29DL320G Primary Vendor-Specific
Extended Query.............................................................................. 33
Flash Command Definitions . . . . . . . . . . . . . . . . 34
Reading Array Data ................................................................34
Reset Command .....................................................................34
Autoselect Command Sequence ............................................34
Enter SecSi Sector/Exit SecSi Sector
Command Sequence ..............................................................34
ProgramCommand Sequence ...............................................35
Figure 4. ProgramOperation.......................................................... 36
Chip Erase Command Sequence ...........................................36
Sector Erase Command Sequence ........................................36
Figure 5. Erase Operation.............................................................. 37
Erase Suspend/Erase Resume Commands ...........................37
Table 22. Am29DL640G and Am29DL320G Command Definitions 38
Flash Write Operation Status . . . . . . . . . . . . . . . 39
DQ7: Data#Polling .................................................................39
Figure 6. Data#Polling Algorithm.................................................. 39
DQ6: Toggle Bit I ....................................................................40
Figure 7. Toggle Bit Algorithm....................................................... 40
DQ2: Toggle Bit II ...................................................................41
Reading Toggle Bits DQ6/DQ2 ...............................................41
DQ5: Exceeded Timng Limts ................................................41
DQ3: Sector Erase Timer .......................................................41
Table 23. Write Operation Status ...................................................42
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 43
Figure 8. MaximumNegative OvershootWaveform...................... 43
Figure 9. MaximumPositive OvershootWaveform........................ 43
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 44
CMOS Compatible .....................................................................44
Figure 10. I
CC1
Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 45
Figure 11. Typical I
vs. Frequency............................................ 45
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 46
Figure 12. Standby Current ISB CMOS......................................... 46
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Test Setup.................................................................... 47
Figure 14. Input Waveforms and Measurement Levels................. 47
Flash AC Characteristics . . . . . . . . . . . . . . . . . . 48
Pseudo SRAMCE#s Timng ......................................................48
Figure 15. Timng Diagramfor Alternating
Between Pseudo SRAM to Flash................................................... 48
Read-Only Operations ..............................................................49
Figure 16. Read Operation Timngs............................................... 49
Hardware Reset (RESET#) .......................................................50
Figure 17. Reset Timngs............................................................... 50
Erase and ProgramOperations .................................................51
Figure 18. ProgramOperation Timngs.......................................... 52
Figure 19. Accelerated ProgramTimng Diagram.......................... 52
Figure 20. Chip/Sector Erase Operation Timngs.......................... 53
Figure 21. Back-to-back Read/Write Cycle Timngs...................... 54
Figure 22. Data# Polling Timngs (During Embedded Algorithms). 54
Figure 23. Toggle Bit Timngs (During Embedded Algorithms)...... 55
Figure 24. DQ2 vs. DQ6................................................................. 55
Temporary Sector Unprotect .....................................................56
Figure 25. Temporary Sector Unprotect Timng Diagram.............. 56
Figure 26. Sector/Sector Block Protect and
Unprotect Timng Diagram............................................................. 57
Alternate CE#f Controlled Erase and ProgramOperations .......58
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
OperationTimngs.......................................................................... 59
Pseudo SRAM AC Characteristics . . . . . . . . . . . 60
Power Up Time ..........................................................................60
Read Cycle ................................................................................60
Figure 28. Pseudo SRAMRead Cycle—Address Controlled......... 60
Figure 29. Pseudo SRAMRead Cycle........................................... 61
Write Cycle ................................................................................62
Figure 30. Pseudo SRAMWrite Cycle—WE#Control................... 62
Figure 31. Pseudo SRAMWrite Cycle—CE1#s Control................ 63
Figure 32. Pseudo SRAMWrite Cycle—
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