參數(shù)資料
型號(hào)： AM50DL128BG
英文描述： Am50DL128BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： Am50DL128BG -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 48/70頁(yè)
文件大小： 1042K
代理商： AM50DL128BG
May 19, 2003
Am50DL9608G
47
P R E L I M I N A R Y
TEST CONDITIONS
Table 24.
Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 k
C
L
6.2 k
3.3 V
Device
Under
Test
Note:
Diodes are IN3064 or equivalent
Figure 13.
Test Setup
Test Condition
All Speed Options
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.0–3.0
V
Input timing measurement
reference levels
1.5
V
Output timing measurement
reference levels
1.5
V
KS000010-PAL
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Output
Measurement Level
Input
Figure 14.
Input Waveforms and Measurement Levels
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