參數資料
型號： AM79C874VC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 網絡接口
英文描述： NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP80
封裝： 12 X 12 MM, PLASTIC, MO-136BAM, TQFP-80
文件頁數： 13/60頁
文件大?。?/td> 869K
代理商： AM79C874VC
Am79C874
13
P R E L I M I N A R Y
MDC
Management Data Clock
This clock is sourced by the MAC and is used to
synchronize MDIO data. When management is not
used, this pin should be tied to ground.
Input
INTR
Interrupt
This pin is used to signal an interrupt to the MAC. The
pin will be forced high or low (normally high impedance)
to signal an interrupt depending upon the value of the
INTR_LEVL bit, MII Register 16, bit 14. The events
which trigger an interrupt can be programmed via the
Interrupt Control Register (Register 17).
Output, High Impedance
TECH_SEL[2:0]
Technology Select
The Technology Select pins, in conjunction with the
ANEGA pin, set the speed and duplex configurations
for the device on the rising edge of reset. These capa-
bilities are reflected in MII Register 1 and MII Register
4. Table 3 lists the possible configurations for the de-
vice. If the input is listed as LOW, the pin should be
pulled to ground via a 10 k resistor on the rising edge
of reset. If the input is listed as HIGH, the pin can be left
unconnected.
Input, Pull-Up
Note:
By
TECH_SEL[2:0] pins and the ANEGA pin, using the
MDC/MDIO management interface pins becomes op-
tional. The device’s speed, duplex, and auto-negotia-
tion capabilities are set via hardware. If the
management interface is used, the registers cannot be
set to a higher capability than the hard-wired setting.
The highest capabilities are Full Duplex, 100 Mbps,
and Auto-Negotiation enabled.
ANEGA
Auto-Negotiation Ability
When this pin is pulled to ground via a 10 k resistor,
on the rising edge of reset, Auto-Negotiation is dis-
abled. When this pin is left unconnected, on the rising
edge of reset, Auto-Negotiation is enabled. Note that
this pin acts in conjunction with Tech_Sel[2:0] on the
rising edge of reset. Refer to Table 3 to determine the
desired configuration for the device.
using
resistors
to
hard
wire
the
Input, Pull-Up
Note:
By
TECH_SEL[2:0] pins and the ANEGA pin, using the
MDC/MDIO management interface pins becomes op-
tional. The device’s speed, duplex, and auto-negotia-
tion capabilities are set via hardware. If the
management interface is used, the registers cannot be
set to a higher capability than the hard-wired setting.
The highest capabilities are Full Duplex, 100 Mbps,
and Auto-Negotiation enabled.
using
resistors
to
hard
wire
the
RPTR
Repeater Mode
This pin should be tied to ground via a 10 k resistor if
repeater mode is to be disabled. When this pin is pulled
high via a 10 k
resistor, repeater mode will be en-
abled. Repeater mode can also enabled via MII Regis-
ter 16, bit 15.
LED Port Pins
LEDRX/LED_SEL
Receive LED/LED Configuration Select
Input
Input/Output, Pull-Up
When this pin is pulled low via a 5 k resistor, on the
rising edge of reset, the advanced LED configuration is
enabled. If there is no pull-down resistor present, on
the rising edge of reset, the standard LED configuration
is enabled.
After the rising edge of reset this pin controls the Re-
ceive LED. This pin toggles between high and low when
data is received. When the device is operating in the
standard LED mode, refer to Table 4 and Figure 5 in the
LED Port Configuration
section. When the device is op-
erating in the advanced LED mode, refer to Table 5 and
Figure 6 in the
LED Port Configuration
section.
LEDCOL/SCRAM_EN
Collision LED/Scrambler Enable
Input/Output, Pull-Up
When this pin is pulled low via a 1-k resistor, on the
rising edge of reset, the scrambler/descrambler is dis-
abled. If no pull-down resistor is present, on the rising
edge of reset, the scrambler/descrambler is enabled.
After the rising edge of reset this pin controls the Colli-
sion LED. This pin toggles between high and low when
there is a collision in half-duplex operation. In full-
duplex operation this pin is inactive. When the device is
operating in the standard LED mode (see LEDRX/LED-
SEL pin description), refer to Table 4 and Figure 5 in the
LED Port Configuration
section. When the device is op-
erating in the advanced LED mode (see LEDRX/LED-
SEL pin description), see Table 5 and Figure 6.
LEDLNK/LED_10LNK/LED_PCSBP_SD
Link LED/7-Wire Link LED/PCSBP Signal Detect
Output
When a link is established in 100BASE-X or
10BASE-T mode, this pin will assume a logic low level.
When a link is established in 7-Wire mode, this pin will
assume a logic high level.
When in PCS Bypass mode, this pin assumes a logic
high level indicating Signal Detect.
Refer to Table 4 and Figure 4 in the
LED Port Configu-
ration
section if the device is operating in the standard
LED mode. See Table 5 and Figure 5 if the device is op-
erating in the advanced LED mode.
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相關代理商/技術參數
參數描述
AM79C874VD 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874VF 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874VI 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874WW 制造商:Advanced Micro Devices 功能描述:8" WAFER, DIE IN WAFER FORM, SINGLE PORT ETHERNET 10/100 - Trays
AM79C875 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver
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