參數(shù)資料
型號(hào): AM79C940KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Media Access Controller for Ethernet (MACE)
中文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP10
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 39/122頁(yè)
文件大?。?/td> 914K
代理商: AM79C940KCW
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)
AMD
39
Am79C940
Data
Receiver
Manchester
Decoder
Noise
Reject
Filter
Carrier
Detect
Circuit
DI
±
SRD
SRDCLK
RXCRS
1616235C-5
Receiver Block Diagram
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width rejec-
tion is proportional to transmit data rate. DC inputs more
negative than minus 100 mV are also suppressed.
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010 to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI
±
, the internal enable signal from the SIA to
controller (RXCRS) is asserted and a clock acquisition
cycle is initiated.
Clock Acquisition
When there is no activity at DI
±
(receiver is idle), the re-
ceive oscillator is phase locked to TCK. The first nega-
tive clock transition (bit cell center of first valid
Manchester “0”) after RXCRS is asserted interrupts the
receive oscillator. The oscillator is then restarted at the
second Manchester “0” (bit time 4) and is phase locked
to it. As a result, the SIA acquires the clock from the
incoming Manchester bit pattern in 4 bit times with a
“1010” Manchester bit pattern.
SRDCLK and SRD are enabled 1/4 bit time after clock
acquisition in bit cell 5 if the ENPLSIO bit is set in the
PLS configuration control register. SRD is at a HIGH
state when the receiver is idle (no SRDCLK). SRD how-
ever, is undefined when clock is acquired and may re-
main HIGH or change to LOW state whenever SRDCLK
is enabled. At 1/4 bit time through bit cell 5, the controller
portion of the MACE device sees the first SRDCLK tran-
sition. This also strobes in the incoming fifth bit to the
SIA as Manchester “1”. SRD may make a transition after
the SRDCLK rising edge bit cell 5, but its state is still un-
defined. The Manchester “1” at bit 5 is clocked to SRD
output at 1/4 bit time in bit cell 6.
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the phase-
locked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage Con-
trolled Oscillator (VCO) are limited to 10% of the phase
difference between BCC and phase-locked clock.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI
±
inputs after
RXCRS is asserted for an end of message. RXCRS de-
asserts 1 to 2 bit times after the last positive transition on
the incoming message. This initiates the end of recep-
tion cycle. The time delay from the last rising edge of the
message to RXCRS deassert allows the last bit to be
strobed by SRDCLK and transferred to the controller
section, but prevents any extra bit(s) at the end of mes-
sage. When IRENA de-asserts (see Receive Timing-
End of Reception (Last Bit = 0) and Receive Timing-End
of Reception (Last Bit = 1) waveform diagrams) an
RXCRS hold off timer inhibits RXCRS assertion for at
least 2 bit times.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI
±
inputs. Input error is
less than
±
35 mV to minimize sensitivity to input rise
and fall time. SRDCLK strobes the data receiver output
at 1/4 bit time to determine the value of the Manchester
bit, and clocks the data out on SRD on the following
SRDCLK. The data receiver also generates the signal
used for phase detector comparison to the internal SIA
voltage controlled oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI
±
) is
externally terminated by two 40.2 ohm
±
1% resistors
and one optional common-mode bypass capacitor, as
shown in the Differential Input Termination diagram
相關(guān)PDF資料
PDF描述
AM79C960 PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C940KI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C940KI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C940VC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C940VC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩)
AM79C940VCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE)