參數(shù)資料
型號(hào)： AM79C940KCW
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Media Access Controller for Ethernet (MACE)
中文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP10
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 59/122頁(yè)
文件大?。?/td> 914K
代理商： AM79C940KCW
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)當(dāng)前第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)
AMD
59
Am79C940
Transmit Retry Count (XMTRC)
The Transmit Retry Count should be read only in re-
sponse to a hardware interrupt request (
INTR
asserted)
when XMTINT is set in the Interrupt Register, or after
XMTSV is set in the Poll Register.The register should be
read before the Transmit Frame Status register. Read-
ing the Transmit Frame Status with XMTSV set will
cause the XMTRC value to be reset. This register is
read only.
(REG ADDR 4)
EXDEF
RES
RES
XMTRC[3–0]
RES
Bit
Name
Description
Bit 3-0
EXDEF
Excessive Defer. The EXDEF bit
will be set if a transmit frame
waited for an excessive period
for transmission. An excessive
defer time is defined in accor-
dance with the following (from
page 34, section 5.2.4.1 of IEEE
Std 802.3h–1990 Layer Manage-
ment):maxDeferTime = {2 x (max
frame size x 8)} bits where
maxFrameSize = 1518 bytes
(from page 68, section 4.4.2.1 of
ANSI/IEEE Std 802.3–1990).
So, the maxDeferTime = 24288
bits = 2
14
+ 2
12
+ 2
11
+ 2
10
+ 2
9
+2
7
+2
6
+2
5
Reserved. Read as zeroes. Al-
ways write as zeroes.
Transmit Retry Count. Contains
the count of the number of retry
attempts made by the MACE de-
vice to transmit the current trans-
mit packet. The value of the
counter will be zero if the first
transmission attempt was suc-
cessful, and a maximum of 15 if
all retry attempts were utilized.
RTRY will be set in Transmit
Frame Status if all 16 attempts
were unsuccessful.
Bit 6–4 RES
Bit 3–0 XMTRC
[3–0]
Receive Frame Control (RCVFC)
(REG ADDR 5)
RES
RES
LLRCV
M/R
RES
ASTRPRCV
RES
RES
Bit
Name
Description
Bit 7–4 RES
Reserved. Read as zeroes. Al-
ways write as zeroes.
Low Latency Receive. A pro-
grammable option to allow ac-
cess to the Receive FIFO before
the 64-byte threshold has been
reached. When set, data can be
read from the RCVFIFO once a
Bit 3
LLRCV
low threshold (12-bytes after
SFD plus synchronization) has
been
exceeded,
RDTREQ
to
RDTREQ
will remain asserted as
long as one read cycle can be
performed on the RCVFIFO
(identical to the burst mode).
Indication of a valid read cycle
from the RCVFIFO will return
DTV
asserted. Reading the
RCVFIFO before data is avail-
able, or while waiting for addi-
tional data once a packet is in
progress will not cause the
RCVFIFO to underflow, and will
be indicated by
DTV
being inva-
lid. The MACE device will no
longer be able to reject runts in
this mode, this responsibility is
transferred to the host system. In
the case of a collided packet
(normal slot time collision or late
collision), the MACE device will
abort the reception, and return
the RCVFS. Note that all colli-
sions in this mode will appear as
late collisions and be reported by
the CLSN bit in the Receive
Status (RCVSTS) byte.
If the host does not keep up with
the incoming receive data, nor-
mal RCVFIFO overflow recovery
is provided.
Match/Reject. The Match/Reject
option sets the criteria for the Ex-
ternal Address Detection Inter-
face. If set, the
EAM/R
pin is
configured as External Address
Match, and is used to signal the
acceptance of a receive frame to
the MACE device. If cleared, the
pin functions as External Ad-
dress Reject and is used to flush
unwanted packets from the Re-
ceive FIFO prior to the first asser-
tion of
RDTREQ
. M/
R
is cleared
by activation of the
RESET
pin or
SWRST bit. When the EADI fea-
ture is disabled, the
EAM/R
pin
must be tied active (low) and all
normal receive address recogni-
tion configurations are supported
(physical, logical and promiscu-
ous). See the section “External
Address Detection Interface” for
additional details.
Reserved. Read as zero. Always
write as zero.
causing
asserted.
be
Bit 2
M/
R
Bit 1
RES
相關(guān)PDF資料
PDF描述
AM79C960 PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C940KI 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:LAN Node Controller
AM79C940KI/W 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:LAN Node Controller
AM79C940VC 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:LAN Node Controller
AM79C940VC/W 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩)
AM79C940VCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*