參數(shù)資料
型號: AM79C940KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Media Access Controller for Ethernet (MACE)
中文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP10
封裝: PLASTIC, QFP-100
文件頁數(shù): 94/122頁
文件大?。?/td> 914K
代理商: AM79C940KCW
AMD
94
Am79C940
AC CHARACTERISTICS (continued)
Parameter
No.
Symbol
GPSI Clock Timing
17
t
STDC
STDCLK period
18
t
STDCL
STDCLK low pulse width
19
t
STDCH
STDCLK high pulse width
20
t
STDCR
STDCLK rise time
21
t
STDCF
STDCLK fall time
22
t
SRDC
SRDCLK period
23
t
SRDCH
SRDCLK HIGH pulse width
24
t
SRDCL
SRDCLK LOW pulse width
25
t
SRDCR
SRDCLK rise time
26
t
SRDCF
SRDCLK fall time
GPSI Timing
70
t
TXEND
STDCLK
delay to
TXEN
71
t
TXENH
TXEN
hold time from STDCLK
72
t
TXDD
STDCLK
delay to TXDAT+
change
73
t
TXDH
TXDAT+ hold time from
STDCLK
74
t
RXDR
RXDAT rise time
75
t
RXDF
RXDAT fall time
76
t
RXDH
RXDAT hold time (SRDCLK
to
RXDAT change)
77
t
RXDS
RXDAT setup time
(RXDAT stable to SRDCLK
)
78
t
CRSL
RXCRS low time
79
t
CLSHI
CLSN high time
80
t
TXH
TXEN
or TXDAT
±
hold time from
CLSN
81
t
CRSH
RXCRS hold time from
SRDCLK
EADI Feature Timing
85
t
DSFBDR
SRDCLK
delay to SF/BD
86
t
DSFBDF
SRDCLK
delay to SF/BD
87
t
EAMRIS
EAM/R
invalid setup prior to
SRDCLK
after SFD
88
t
EAMS
EAM
setup to SRDCLK
at bit 6
of Source Address byte 1
(match packet)
89
t
EAMR
L
EAM/R
low time
90
t
SFBDHIH
SF/BD high hold from last
SRDCLK
91
t
EARS
EAR
setup to SRDCLK
at bit 6
of message byte 64
(reject normal packet)
Parameter Description
Test Conditions
Min (ns)
Max (ns)
99
45
45
101
See Note 1
See Note 1
See Note 1
5
5
85
38
38
115
See Note 1
See Note 1
5
5
(C
L
=50 pF)
(C
L
=50 pF)
(C
L
=50 pF)
70
5
70
(C
L
=50 pF)
5
See Note 1
See Note 1
8
8
25
0
t
STDC
+20
t
STDC
+30
32*t
STDC
96*t
STDC
0
20
20
–150
0
200
100
0
Note:
1. Not tested but data available upon request.
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