- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C970AKCW (ADVANCED MICRO DEVICES INC) PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C970AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 71/219頁(yè) |
| 文件大小： | 1065K |
| 代理商： | AM79C970AKCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)當(dāng)前第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)
P R E L I M I N A R Y
AMD
71
Am79C970A
the PCnet-PCI II controller returns ownership for the last
buffer of the first frame.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, trans-
mit status of the current buffer will be immediately up-
dated. If the buffer does not contain the end of packet,
the PCnet-PCI II controller will skip over the rest of the
frame which experienced the error. This is done by re-
turning to the polling microcode where the PCnet-PCI II
controller will clear the OWN bit for all descriptors with
OWN = 1 and STP = 0 and continue in like manner until a
descriptor with OWN = 0 (no more transmit frames in the
ring) or OWN = 1 and STP = 1 (the first buffer of a new
frame) is reached.
At the end of any transmit operation, whether successful
or with errors, immediately following the completion of
the descriptor updates, the PCnet-PCI II controller will
always perform another polling operation. As described
earlier, this polling operation will begin with a check of
the current RDTE, unless the PCnet-PCI II controller al-
ready owns that descriptor. Then the PCnet-PCI II con-
troller will poll the next TDTE. If the transmit descriptor
OWN bit has a ZERO value, the PCnet-PCI II controller
will resume incrementing the poll time counter. If the
transmit descriptor OWN bit has a value of ONE, the
PCnet-PCI II controller will begin filling the FIFO with
transmit data and initiate a transmission. This end-of-
operation poll coupled with the TDTE lookahead opera-
tion allows the PCnet-PCI II controller to avoid inserting
poll time counts between successive transmit frames.
By default, whenever the PCnet-PCI II controller com-
pletes a transmit frame (either with or without error) and
writes the status information to the current descriptor,
then the TINT bit of CSR0 is set to indicate the comple-
tion of a transmission. This causes an interrupt signal if
the IENA bit of CSR0 has been set and the TINTM bit of
CSR3 is cleared. The PCnet-PCI II controller provides
two modes to reduce the number of transmit interrupts.
The interrupt of a successfully transmitted frame can be
suppressed by setting TINTOKD (CSR5, bit 15) to ONE.
Another mode, which is enabled by setting LTINTEN
(CSR5, bit 14) to ONE, allows suppression of interrupts
for successful transmissions for all but the last frame in
a sequence.
Receive Descriptor Table Entry
If the PCnet-PCI II controller does not own both the cur-
rent and the next Receive Descriptor Table Entry
(RDTE) then the PCnet-PCI II controller will continue to
poll according to the polling sequence described above.
If the receive descriptor ring length is one, then there is
no next descriptor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the PCnet-PCI II controller then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-PCI II controller retains ownership of the cur-
rent and the next RDTE.
When receive activity is present on the channel, the
PCnet-PCI II controller waits for the complete address
of the message to arrive. It then decides whether to ac-
cept or reject the frame based on all active addressing
schemes. If the frame is accepted the PCnet-PCI II con-
troller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the
current buffer.
If ownership is lacking, the PCnet-PCI II controller will
immediately perform a final poll of the current RDTE. If
ownership is still denied, the PCnet-PCI II controller has
no buffer in which to store the incoming message. The
MISS bit will be set in CSR0 and the Missed Frame
Counter (CSR112) will be incremented. An interrupt will
be generated if IENA (CSR0, bit 6) is set to ONE and
MISSM (CSR3, bit 12) is cleared to ZERO. Another
poll of the current RDTE will not occur until the frame
has finished.
If the PCnet-PCI II controller sees that the last poll
(either a normal poll, or the final effort described in the
above paragraph) of the current RDTE shows valid own-
ership, it proceeds to a poll of the next RDTE. Following
this poll, and regardless of the outcome of this poll,
transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive
descriptor, the PCnet-PCI II controller will continue to
perform receive data DMA transfers to the first buffer. If
the frame length exceeds the length of the first buffer,
and the PCnet-PCI II controller does not own the second
buffer, ownership of the current descriptor will be
passed back to the system by writing a ZERO to
the OWN bit of RMD1 and status will be written
indicating buffer (BUFF = 1) and possibly overflow
(OFLO = 1) errors.
If the frame length exceeds the length of the first (cur-
rent) buffer, and the PCnet-PCI II controller does own
the second (next) buffer, ownership will be passed back
to the system by writing a ZERO to the OWN bit of
RMD1 when the first buffer is full. The OWN bit is the
only bit modified in the descriptor. Receive data
transfers to the second buffer may occur before the
PCnet-PCI II controller proceeds to look ahead to the
ownership of the third buffer. Such action will depend
upon the state of the FIFO when the OWN bit has been
updated in the first descriptor. In any case, lookahead
will be performed to the third buffer and the information
gathered will be stored in the chip, regardless of the
state of the ownership bit.
This activity continues until the PCnet-PCI II controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The PCnet-PCI II controller will subsequently
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVC\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述: |
| AM79C970AVC-G | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。