- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C972BKIW (ADVANCED MICRO DEVICES INC) PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C972BKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 23/130頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BKIW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
Am79C972
23
General Purpose Serial Interface
CLSN
Collision
CLSN is an input that indicates a collision has occurred
on the network.
Input
Note:
The CLSN pin is multiplexed with the COL pin.
RXCLK
Receive Clock
RXCLK is an input. The rising edges of the RXCLK sig-
nal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.
Input
Note:
The RXCLK pin is multiplexed with the RX_CLK
pin.
RXDAT
Receive Data
RXDAT is an input. The rising edges of the RXCLK sig-
nal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.
Input
Note:
The RXDAT pin is multiplexed with the RX_ER
pin.
RXEN
Receive Enable
RXEN is an input. When this signal is HIGH, it indicates
to the core logic that the data on the RXDAT input pin
is valid.
Input
Note:
The RXEN pin is multiplexed with the CRS pin.
TXCLK
Transmit Clock
TXCLK is an input that provides a clock signal for MAC
activity, both transmit and receive. The rising edges of
the TXCLK can be used to validate TXDAT output data.
Input
Note:
The TXCLK pin is multiplexed with the TX_CLK
pin.
TXDAT
Transmit Data
TXDAT is an output that provides the serial bit stream
for transmission, including preamble, SFD, data, and
FCS field, if applicable.
Output
Note:
The TXDAT pin is multiplexed with the TXD[0]
pin.
TXEN
Transmit Enable
TXEN is an output that provides an enable signal for
transmission. Data on the TXDAT pin is not valid unless
the TXEN signal is HIGH.
Output
Note:
The TXEN pin is multiplexed with the TX_EN
pin.
External Address Detection Interface
EAR
External Address Reject Low
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the re-
sult of this check will be OR
’
d with the value on the EAR
pin. The EAR pin is defined as REJECT. The pin value
is OR
’
d with the internal address detection result to de-
termine if the current frame should be accepted or re-
jected.
Input
The EAR pin
must not
be left unconnected, it should
be tied to VDD through a 10-k
±
5% resistor.
When RST is active, EAR is an input for NAND tree
testing
.
SFBD
Start Frame-Byte Delimiter
For the GPSI port during External Address Detec-
tion:
Output
An initial rising edge on the SFBD signal indicates that
a start of frame delimiter has been detected. The serial
bit stream will follow on the SRD signal, commencing
with the destination address field. SFBD will go high for
4 bit times (400 ns when operating at 10 Mbps) after
detecting the second
“
1
”
in the SFD (Start of Frame De-
limiter) of a received frame. SFBD will subsequently
toggle every 4 bit times (1.25 MHz frequency when op-
erating at 10 Mbps) with each rising edge indicating the
first bit of each subsequent byte of the received serial
bit stream.
For the External PHY attached to the Media Inde-
pendent Interface during External Address Detec-
tion:
An initial rising edge on the SFBD signal indicates that
a start of valid data is present on the RXD[3:0] pins.
SFBD will go high for one nibble time (400 ns when op-
erating at 10 Mbps and 40 ns when operating at 100
Mbps) one RX_CLK period after RX_DV has been as-
serted and RX_ER is deasserted and the detection of
the SFD (Start of Frame Delimiter) of a received frame.
Data on the RXD[3:0] will be the start of the destination
address field. SFBD will subsequently toggle every nib-
ble time (1.25 MHz frequency when operating at 10
Mbps and 12.5 MHz frequency when operating at 100
Mbps) indicating the first nibble of each subsequent
byte of the received nibble stream. The RX_CLK
should be used in conjunction with the SFBD to latch
the correct data for external address matching. SFBD
will be active only during frame reception.
Note:
The SFBD pin is multiplexed with the EESK and
LED1 pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972 | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C974 | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C974KCW | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972BVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVC\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray 制造商:Advanced Micro Devices 功能描述:5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| AM79C972BVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVD\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。