參數(shù)資料
型號: AM79C972BKIW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述: 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁數(shù): 39/130頁
文件大?。?/td> 1580K
代理商: AM79C972BKIW
Am79C972
39
Figure 17.
Disconnect Without Data Transfer
RTABORT (PCI Status register, bit 12) will be set to
indicate that the Am79C972 controller has received a
target abort. In addition, SINT (CSR5, bit 11) will be set
to 1. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to 1. This mechanism
can be used to inform the driver of the system error. The
host can read the PCI Status register to determine the
exact cause of the interrupt.
Master Initiated Termination
There are three scenarios besides normal completion
of a transaction where the Am79C972 controller will
terminate the cycles it produces on the PCI bus.
Preemption During Non-Burst Transaction
When the Am79C972 controller performs multiple non-
burst transactions, it keeps REQ asserted until the as-
sertion of FRAME for the last transaction. When GNT
is removed, the Am79C972 controller will finish the cur-
rent transaction and then release the bus. If it is not the
last transaction, REQ will remain asserted to regain
bus ownership as soon as possible. See Figure 19.
Preemption During Burst Transaction
When the Am79C972 controller operates in burst
mode, it only performs a single transaction per bus
mastership period, where
transaction
is defined as one
address phase and one or multiple data phases. The
central arbiter can remove GNT at any time during the
transaction. The Am79C972 controller will ignore the
deassertion of GNT and continue with data transfers,
as long as the PCI Latency Timer is not expired. When
the Latency Timer is 0 and GNT is deasserted, the
Am79C972 controller will finish the current data phase,
deassert FRAME, finish the last data phase, and re-
lease the bus. If EXTREQ (BCR18, bit 8) is cleared to
0, it will immediately assert REQ to regain bus owner-
ship as soon as possible. If EXTREQ is set to 1, REQ
will stay asserted.
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
REQ
GNT
PAR
DEVSEL is sampled
STOP
ADDRi
0000
0111
PAR
0111
2
3
4
5
6
7
8
9
11
10
ADDRi
DATA
PAR
1
21485C-20
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