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參數(shù)資料
| 型號(hào)： | AM79C972BKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 91/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BKIW |
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Am79C972
91
Reset
There are four different types of RESET operations that
may be performed on the Am79C972 device,
H_RESET, S_RESET, STOP, and POR. The following
is a description of each type of RESET operation.
H_RESET
Hardware Reset (H_RESET) is an Am79C972 reset
operation that has been created by the proper asser-
tion of the RST pin of the Am79C972 device while the
PG pin is HIGH. When the minimum pulse width timing
as specified in the RST pin description has been satis-
fied, then an internal reset operation will be performed.
H_RESET will program most of the CSR and BCR reg-
isters to their default value. Note that there are several
CSR and BCR registers that are undefined after
H_RESET. See the sections on the individual registers
for details.
H_RESET will clear most of the registers in the PCI
configuration space. H_RESET will cause the micro-
code program to jump to its reset state. Following the
end of the H_RESET operation, the Am79C972 con-
troller will attempt to read the EEPROM device through
the EEPROM interface.
H_RESET will clear DWIO (BCR18, bit 7) and the
Am79C972 controller will be in 16-bit I/O mode after
the reset operation. A DWord write operation to the
RDP (I/O offset 10h) must be performed to set the de-
vice into 32-bit I/O mode.
S_RESET
Software Reset (S_RESET) is an Am79C972 reset op-
eration that has been created by a read access to the
Reset register, which is located at offset 14h in Word
I/O mode or offset 18h in DWord I/O mode from the
Am79C972 I/O or memory mapped I/O base address.
S_RESET will reset all of or some portions of CSR0, 3,
4, 15, 80, 100, and 124 to default values. For the iden-
tity of individual CSRs and bit locations that are af-
fected by S_RESET, see the individual CSR register
descriptions. S_RESET will not affect any PCI configu-
ration space location. S_RESET will not affect any of
the BCR register values. S_RESET will cause the mi-
crocode program to jump to its reset state. Following
the end of the S_RESET operation, the Am79C972
controller will not attempt to read the EEPROM device.
After S_RESET, the host must perform a full re-initial-
ization of the Am79C972 controller before starting net-
work activity. S_RESET will cause REQ to deassert
immediately. STOP (CSR0, bit 2) or SPND (CSR5, bit
0) can be used to terminate any pending bus master-
ship request in an orderly sequence.
S_RESET terminates all network activity abruptly. The
host can use the suspend mode (SPND, CSR5, bit 0)
to terminate all network activity in an orderly sequence
before issuing an S_RESET.
STOP
A STOP reset is generated by the assertion of the
STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,
when the stop bit currently has a value of 0, will initiate
a STOP reset. If the STOP bit is already a 1, then writ-
ing a 1 to the STOP bit will not generate a STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4
to default values. For the identity of individual CSRs
and bit locations that are affected by STOP, see the in-
dividual CSR register descriptions. STOP will not affect
any of the BCR and PCI configuration space locations.
STOP will cause the microcode program to jump to its
reset state. Following the end of the STOP operation,
the Am79C972 controller will not attempt to read the
EEPROM device.
Note:
STOP will not cause a deassertion of the REQ
signal, if it happens to be active at the time of the write
to CSR0. The Am79C972 controller will wait until it
gains bus ownership and it will first finish all scheduled
bus master accesses before the STOP reset is exe-
cuted.
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
minate all network activity in an orderly sequence be-
fore setting the STOP bit.
Power on Reset
Power on Reset (POR) is generated when the
Am79C972 controller is powered up. POR generates a
hardware reset (H_RESET). In addition, it clears some
bits that H_RESET does not affect.
Software Access
PCI Configuration Registers
The Am79C972 controller implements the 256-byte
configuration space as defined by the PCI specification
revision 2.1. The 64-byte header includes all registers
required to identify the Am79C972 controller and its
function. Additionally, PCI Power Management Inter-
face registers are implemented at location 40h - 47h.
The layout of the Am79C972 PCI configuration space
is shown in Table 16.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow
little endian byte ordering. All write accesses to Re-
served locations have no effect; reads from these loca-
tions will return a data value of 0.
I/O Resources
The Am79C972 controller requires 32 bytes of address
space for access to all the various internal registers as
well as to some setup information stored in an external
serial EEPROM. A software reset port is available, too.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972BVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVC\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray 制造商:Advanced Micro Devices 功能描述:5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| AM79C972BVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVD\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray |
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