參數(shù)資料
型號(hào): AM79C973KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述: 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 172/304頁(yè)
文件大小: 2092K
代理商: AM79C973KCW
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172
Am79C973/Am79C975
P R E L I M I N A R Y
will always operate in the half-du-
plex mode. When FDEN is set,
the Am79C973/Am79C975 con-
troller will operate in full-duplex
mode.
Do not set this bit when
Auto-Negotiation is enabled
.
Read/Write accessible always.
FDEN is reset to 0 by H_RESET,
and is unaffected by S_RESET
and the STOP bit.
BCR16: I/O Base Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-5
IOBASEL
Reserved
H_RESET, the value of these bits
will be undefined. The settings of
these bits will have no effect on
any Am79C973/Am79C975 con-
troller function. It is only included
for software compatibility with
other PCnet family devices.
locations.
After
Read/Write accessible always.
IOBASEL is not affected by
S_RESET or STOP.
4-0
RES
Reserved locations. Written as
zeros, read as undefined.
BCR17: I/O Base Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IOBASEU
Reserved
H_RESET, the value in this regis-
ter will be undefined. The settings
of this register will have no effect
on any Am79C973/Am79C975
controller function. It is only in-
cluded for software compatibility
with other PCnet family devices.
locations.
After
Read/Write accessible always.
IOBASEU is not affected by
S_RESET or STOP.
BCR18: Burst and Bus Control Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 ROMTMG
Expansion ROM Timing. The val-
ue of ROMTMG is used to tune
the timing for all EBDATA
(BCR30) accesses to Flash/
EPROM as well as all Expansion
ROM accesses to Flash/EPROM.
ROMTMG, during read opera-
tions, defines the time from when
the Am79C973/Am79C975 con-
troller drives the lower 8 or 16 bits
of the Expansion Bus Address
bus to when the Am79C973/
Am79C975 controller latches in
the data on the 8 or 16 bits of the
Expansion Bus Data inputs.
ROMTMG, during write opera-
tions, defines the time from when
the Am79C973/Am79C975 con-
troller drives the lower 8 or 16 bits
of the Expansion Bus Data to
when the EBWE and EROMCS
deassert.
The register value specifies the
time in number of clock cycles +1
according to Table 31.
Note
: Programming ROMTNG
with a value of 0 is not permitted.
The access time for the Expan-
sion ROM or the EBDATA
(BCR30) device (t
ACC
) during
read operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA_EBA[7:0]
outputs (t
v_A_D
) and by subtract-
ing the input to clock setup time
for the EBD[7:0] inputs (t
s_D
)
from the time defined by ROMT-
MG:
t
ACC
= ROMTMG * CLK period
*CLK_FAC - (t
v_A_D
) - (t
s_D
)
Table 31. ROMTNG Programming Values
ROMTMG (bits 15-12)
1h<=n <=Fh
No. of Expansion Bus Cycles
n+1
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