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參數(shù)資料
| 型號： | AM79C973KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 76/304頁 |
| 文件大小： | 2092K |
| 代理商： | AM79C973KCW |
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76
Am79C973/Am79C975
P R E L I M I N A R Y
CSR12 to CSR14). The byte ordering is such that the
first byte received from the network (after the SFD)
must match the least significant byte of CSR12
(PADR[7:0]), and the sixth byte received must match
the most significant byte of CSR14 (PADR[47:40]).
When DRCVPA (CSR15, bit 13) is set to 1, the
Am79C973/Am79C975 controller will not accept uni-
cast frames.
If the incoming frame is multicast, the Am79C973/
Am79C975 controller performs a calculation on the
contents of the destination address field to determine
whether or not to accept the frame. This calculation is
explained in the section that describes the Logical Ad-
dress Filter (LADRF).
When all bits of the LADRF registers are 0, no multicast
frames are accepted, except for broadcast frames.
Although broadcast frames are classified as special
multicast frames, they are treated differently by the
Am79C973/Am79C975 controller hardware. Broadcast
frames are always accepted, except when DRCVBC
(CSR15, bit 14) is set and there is no Logical Address
match.
None of the address filtering described above applies
when the Am79C973/Am79C975 controller is operat-
ing in the promiscuous mode. In the promiscuous
mode, all properly formed packets are received, re-
gardless of the contents of their destination address
fields. The promiscuous mode overrides the Disable
Receive Broadcast bit (DRCVBC bit l4 in the MODE
register) and the Disable Receive Physical Address bit
(DRCVPA, CSR15, bit 13).
The Am79C973/Am79C975 controller operates in pro-
miscuous mode when PROM (CSR15, bit 15) is set.
In addition, the Am79C973/Am79C975 controller pro-
vides the External Address Detection Interface (EADI)
to allow external address filtering. See the section
Ex-
ternal Address Detection Interface
for further detail.
The receive descriptor entry RMD1 contains three bits
that indicate which method of address matching
caused the Am79C973/Am79C975 controller to accept
the frame. Note that these indicator bits are only avail-
able when the Am79C973/Am79C975 controller is pro-
grammed to use 32-bit structures for the descriptor
entries (BCR20, bit 7-0, SWSTYLE is set to 2 or 3).
PAM (RMD1, bit 22) is set by the Am79C973/
Am79C975 controller when it accepted the received
frame due to a match of the frame
’
s destination ad-
dress with the content of the physical address register.
LAFM (RMD1, bit 21) is set by the Am79C973/
Am79C975 controller when it accepted the received
frame based on the value in the logical address filter
register.
BAM (RMD1, bit 20) is set by the Am79C973/
Am79C975 controller when it accepted the received
frame because the frame
’
s destination address is of the
type
’
Broadcast
’
.
If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM,
but not LAFM will be set when a Broadcast frame is re-
ceived, even if the Logical Address Filter is pro-
grammed in such a way that a Broadcast frame would
pass the hash filter. If DRCVBC is set to 1 and the Log-
ical Address Filter is programmed in such a way that a
Broadcast frame would pass the hash filter, LAFM will
be set on the reception of a Broadcast frame.
When the Am79C973/Am79C975 controller operates
in promiscuous mode and none of the three match bits
is set, it is an indication that the Am79C973/Am79C975
controller only accepted the frame because it was in
promiscuous mode.
When the Am79C973/Am79C975 controller is not pro-
grammed to be in promiscuous mode, but the EADI in-
terface is enabled, then when none of the three match
bits is set, it is an indication that the Am79C973/
Am79C975 controller only accepted the frame because
it was not rejected by driving the EAR pin LOW within
64 bytes after SFD.
See Table 7 for receive address matches.
Table 7. Receive Address Match
Automatic Pad Stripping
During reception of an IEEE 802.3 frame, the pad field
can be stripped automatically. Setting ASTRP_RCV
(CSR4, bit 0) to 1 enables the automatic pad stripping
feature. The pad field will be stripped before the frame
is passed to the FIFO, thus preserving FIFO space for
additional frames. The FCS field will also be stripped,
since it is computed at the transmitting station based on
the data and pad field characters, and will be invalid for
a receive frame that has had the pad characters
stripped.
PAM
LAF
M
BAM
DRC
VBC
Comment
0
0
0
X
Frame accepted due to
PROM = 1 or no EADI
reject
Physical address match
Logical address filter
match;
frame is not of type
broadcast
Logical address filter
match;
frame can be of type
broadcast
Broadcast frame
1
0
0
X
0
1
0
0
0
1
0
1
0
0
1
0
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| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973VCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C974 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C974KC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C974KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
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