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參數(shù)資料
| 型號： | AM79C973KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 249/304頁 |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C973KCW |
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Am79C973/Am79C975
249
P R E L I M I N A R Y
of the Block Write command specifies the byte count.
The byte count value is ignored by the Am79C975 con-
troller. The device is capable of receiving any amount
of data even passed the limit of 32 bytes as defined by
the SMB specification. Since the Am79C975 controller
is the receiver of all data transfers, it must acknowledge
each byte by driving the MDATA line LOW for 1 bit time
(A). The master indicates the termination of the Block
Write command with the assertion of the STOP condi-
tion (P).
Note that the Am79C975 controller does not validate
the register address specified in the Block Write com-
mand. A Block Write command to a register other than
the Transmit Data port or the Receive Pattern RAM
Data port may cause unexpected reprogramming of an
SMIU register. The Am79C975 controller also does not
check the length of the Block Write command. The
master must make sure that the Transmit Data memory
or the Receive Pattern RAM are not written beyond
their respective length.
Key:
Figure 74. Block Write Command
Block Read Command
The Block Read command is used to read data from
the SMIU Receive Data memory. This command is
more complex compared to the Block Write command,
since it involves a change in the direction of the data
transfer. The command starts with the START condition
(S). The next 7 bits are the slave address of the
Am79C975 controller, followed by a 0 bit to indicate that
the data transfer starts with a write operation from the
master to the Am79C975 controller (W). The
Am79C975 controller must acknowledge the first byte
by driving MDATA LOW for 1 bit time (A). The next byte
specifies the address of the SMIU register (MReg) that
is accessed, followed by another ACK from the
Am79C975 controller. The address of the Receive
Data port (40), is the only valid value for the MReg ad-
dress. The master initiates the turn-around of the trans-
fer direction by asserting a repeated START condition,
followed by the repeated 7-bit slave address. This time,
the Read/Write bit is set to 1 to indicate that the next
bytes of data are driven by the Am79C975 controller
(R). The Am79C975 controller acknowledges the
transfer and then continues driving the MDATA line.
The first byte is the byte count indicating how many
bytes of data will follow. The byte count field will indi-
cate 32 in all but the last transaction, in which the byte
count field will indicate the remaining bytes of the
frame. This time, the ACK is generated by the master,
since he is the receiver of the data. Receive data will
follow. Being the receiver, the master must ACK each
byte by driving the MDATA line LOW for 1 bit time. The
last byte, however, must be followed by a NACK (N) to
force the Am79C975 controller to stop driving the
MDATA line. The Am79C975 device is capable of a
block read past the 32 byte limit that is indicated in the
byte count field. If the host does not assert NACK after
the 32
nd
byte, the Am79C975 controller will continue
driving receive data onto the MDATA line until the host
asserts NACK. If the master runs out of storage space
for the incoming data, he can abort the data transfer
after any byte by asserting NACK. The Block Read
command terminates with the assertion of the STOP
condition (P) by the master.
Note:
The Am79C975 controller does not validate the
register address specified in the Block Read command.
A Block Read command to a register other than the Re-
ceive Data port will yield unexpected data. The master
must also make sure to only issue a Block Read com-
mand when there is data left in the Receive Data mem-
ory.
1
7
1
1
8
1
8
1
S
Slave Address
W
A
MReg Address
A
Byte Count N
A
8
1
8
1
1
Data Byte 1
A
…
.
Data Byte N
A
P
Master to Am79C975 controller
Am79C975 controller to Master
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C976 | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KIW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973VCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C974 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C974KC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C974KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
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