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參數(shù)資料
| 型號： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 136/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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AMD
A M E N D M E N T
2
Am79C974
Page 19
(Reprinted as page 9 of this amendment)
PIN DESCRIPTION,
GNTA
Add after the second paragraph:
The Am79C974 supports bus parking. When the PCI bus is idle and the system arbiter asserts
GNTA
without an active
REQA
from the Am79C974 controller, the Am79C794 will actively drive the AD[31:00], C/
BE
[3:0], and PAR lines.
Page 20
Note that
INTA
and
INTB
are both open drain pins.
Page 24
Note that
ATN
is open drain.
Page 25
The number of each type of power pin is incorrect. The numbers should be:
— V
DD
/DV
DD
, Digital Power, 5 pins
— V
DDB
/V
DDBS
, I/O Buffer Power, 5 pins
— V
SS
/DV
SS
Digital Ground, 9 pins
— V
SSB
/V
SSBS
, I/O Buffer Ground, 11 pins
Page 30
The second sentence should read, “It is a single cycle, non-burst 8-bit, 16-bit, or 32-bit transfer which is initiated by the
host CPU.” (The original omitted “8-bit”).
Page 32
(Reprinted as page 10 of this amendment)
In Figure 6, data on the AD lines should be driven during clock 6 and the second instance of PAR should be driven
during clock 7. In each case this is one cycle earlier than what is shown in the figure.
Page 35
Line 2, change “type 15” to
“type 14”
.
Page 39
(Reprinted as page 11 of this amendment)
Replace the last two sentences with the following:
“For SCSI, when target aborts,
INTA
will not be asserted, but the ABORT bit (bit 2 of the DMA status register at offset
54h) is set. For either Ethernet or SCSI a target abort causes RTABORT (bit 12) of the status register in the appropriate
PCI configuration space to be set.” (The original stated that
INTA
will be asserted.)
Page 42
(Reprinted as page 12 of this amendment)
Replace the last sentence with the following:
“For SCSI, when the master aborts,
INTA
will not be asserted, but the ABORT bit (bit 2 of the DMA status register at
offset 54h) is set. For either Ethernet or SCSI a master abort causes RMABORT (bit 13) of the status register in the
appropriate PCI configuration space to be set.” (The original stated that
INTA
will be asserted.)
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PDF描述 |
|---|---|
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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