- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C974KCW (ADVANCED MICRO DEVICES INC) PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 55/153頁(yè) |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
P R E L I M I N A R Y
AMD
55
Am79C974
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI
±
inputs. This
collision signal passes through an input stage which de-
tects signal levels and pulse duration. When the signal is
detected by the MENDEC it sets the internal collision
signal HIGH. The condition continues for approximately
1.5 bit times after the last LOW-to-HIGH transition on
CI
±
.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in the
pattern.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of Jitter Han-
dling is:
The peak deviation approaching or crossing 1/4 bit
cell position from nominal input transition, for which
the MENDEC section will properly decode data.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which effec-
tively connects the DTE to a MAU. The differential inter-
face provided by the Am79C974 controller is fully
compliant to Section 7 of ISO 8802-3 (ANSI/IEEE
802.3).
After the Am79C974 controller initiates a transmission it
will expect to see data “l(fā)ooped-back” on the DI
±
pair
(when the AUI port is selected). This will internally gen-
erate a “carrier sense”, indicating that the integrity of the
data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted at least 6 bit times before the last
transmitted bit on DO
±
(when using the AUI port). If “car-
rier sense” does not become active in response to the
data transmission, or becomes inactive before the end
of transmission, the loss of carrier (LCAR) error bit will
be set in the Transmit Descriptor Ring (TMD2, bit 27) af-
ter the frame has been transmitted.
Twisted-Pair Transceiver (T-MAU)
The T-MAU implements the Medium Attachment Unit
(MAU) functions for the Twisted-Pair Medium, as speci-
fied by the supplement to ISO 8802-3 (IEEE/ANSI
802.3) standard (Type 10BASE-T). The T-MAU pro-
vides twisted pair driver and receiver circuits, including
on-board transmit digital predistortion and receiver
squelch and a number of additional features including
Link Status indication, Automatic Twisted-Pair Receive
Polarity Detection/Correction and Indication, Receive
Carrier Sense, Transmit Active and Collision Present
indication.
Twisted-Pair Transmit Function
The differential driver circuitry in the TXD
±
and TXP
±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted-Pair cable, as specified
by the 10BASE-T supplement to the ISO 8802-3 (IEEE/
ANSI 802.3) Standard. The transmit function for data
output meets the propagation delays and jitter specified
by the standard.
Twisted-Pair Receive Function
The receiver complies with the receiver specifications of
the ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Stan-
dard, including noise immunity and received signal re-
jection criteria (‘Smart Squelch’). Signals meeting these
criteria appearing at the RXD
±
differential input pair are
routed to the MENDEC. The receiver function meets the
propagation delays and jitter requirements specified by
the standard. The receiver squelch level drops to half its
threshold value after unsquelch to allow reception of
minimum amplitude signals and to offset carrier fade in
the event of worst case signal attenuation and crosstalk
noise conditions.
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Inter-
face (MDI). Filter and transformer loss are not specified.
The T-MAU receiver squelch levels are defined to ac-
count for a 1 dB insertion loss at 10 MHz, which is typical
for the type of receive filters/transformers employed.
Normal 10BASE-T compatible receive thresholds are
employed when the LRT bit (CSR15[9]) is LOW. When
the LRT bit is set (HIGH), the Low Receive Threshold
option is invoked, and the sensitivity of the T-MAU re-
ceiver is increased. This allows longer line lengths to be
employed, exceeding the 100 m target distance of nor-
mal 10BASE-T (assuming typical 24 AWG cable). The
increased receiver sensitivity compensates for the in-
creased signal attenuation caused by the additional
cable distance.
However, making the receiver more sensitive means
that it is also more susceptible to extraneous noise, pri-
marily caused by coupling from co-resident services
(crosstalk). For this reason, it is recommended that
when using the Low Receive Threshold option that the
service should be installed on 4-pair cable only. Multi-
pair cables within the same outer sheath have lower
crosstalk attenuation, and may allow noise emitted from
adjacent pairs to couple into the receive pair, and be of
sufficient amplitude to falsely unsquelch the T-MAU.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。