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參數(shù)資料
| 型號： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 46/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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AMD
P R E L I M I N A R Y
46
Am79C974
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity be-
ing performed by the Am79C974 controller, then the
Am79C974 controller will periodically poll the current re-
ceive and transmit descriptor entries in order to ascer-
tain their ownership. If the DPOLL bit in CSR4 is set,
then the transmit polling function is disabled.
A typical polling operation consists of the following: The
Am79C974 controller will use the current receive de-
scriptor address stored internally to vector to the appro-
priate Receive Descriptor Table Entry (RDTE). It will
then use the current transmit descriptor address (stored
internally) to vector to the appropriate Transmit Descrip-
tor Table Entry (TDTE). The accesses will be made in
the following order: RMD1, then RMD0 of the current
RDTE during one bus arbitration, and after that, TMD1,
then TMD0 of the current TDTE during a second bus ar-
bitration. All information collected during polling activity
will be stored internally in the appropriate CSRs. (i.e.
CSR18, CSR19, CSR20, CSR21, CSR40, CSR42,
CSR50, CSR52). UnOWNed descriptor status will be in-
ternally ignored.
A typical receive poll is the product of the following
conditions:
1. Am79C974 controller does not possess ownership
of the current RDTE and the poll time has elapsed
and RXON=1 (CSR0, bit 5), or
2. Am79C974 controller does not possess ownership
of the next RDTE the poll time has elapsed and
If RXON=0 the Am79C974 controller will never poll
RDTE locations.
The ideal system should always have at least one RDTE
available for the possibility of an unpredictable receive
event. (This condition is not a requirement. If this condi-
tion is not met, it simply means that frames will be
missed by the system because there was no buffer
space available.) But the typical system usually has at
least one or two RDTEs available for the possibility of an
unpredictable receive event. Given that this condition is
satisfied, the current and next RDTE polls are rarely
seen and hence, the typical poll operation simply con-
sists of a check of the status of the current TDTE. When
there is only one RDTE (because the RLEN was set to
ZERO), then there is no “next RDTE” and ownership of
“next RDTE” cannot be checked. If there is at least one
RDTE, the RDTE poll will rarely be seen and the typical
poll operation simply consists of a check of the
currentTDTE.
A typical transmit poll is the product of the following
conditions:
1. Am79C974 controller does not possess ownership
of the current TDTE and
DPOLL=0 (CSR4, bit 2) and
TXON=1 (CSR0, bit 4) and
the poll time has elapsed, or
2. Am79C974 controller does not possess ownership
of the current TDTE and
DPOLL=0 and
TXON=1 and
a frame has just been received, or
3. Am79C974 controller does not possess ownership
of the current TDTE and
DPOLL=0 and
TXON=1 and
a frame has just been transmitted.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately
perform a polling operation. If RDTE ownership has not
been previously established, then an RDTE poll will be
performed ahead of the TDTE poll. If the microcode is
not executing the poll counting code when the TDMD bit
is set, then the demanded poll of the TDTE will be de-
layed until the microcode returns to the poll
countingcode.
The user may change the poll time value from the de-
fault of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47). Note that if a non–
default value is desired, then a strict sequence of setting
the INIT bit in CSR0, waiting for the IDON bit in CSR0,
then writing to CSR47, and then setting STRT in CSR0
must be observed, otherwise the default value will not
be overwritten. See the CSR47 section for details.
Transmit Descriptor Table Entry (TDTE)
If, after a TDTE access, the Am79C974 controller finds
that the OWN bit of that TDTE is not set, then the
Am79C974 controller resumes the poll time count and
reexamines the same TDTE at the next expiration of the
poll time count.
If the OWN bit of the TDTE is set, but Start of Frame
(STP) bit is not set, the Am79C974 controller will imme-
diately request the bus in order to reset the OWN bit of
this descriptor. (This condition would normally be found
following a LCOL or RETRY error that occurred in the
middle of a transmit frame chain of buffers.) After reset-
ting the OWN bit of this descriptor, the Am79C974 con-
troller will again immediately request the bus in order to
access the next TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be reset. In the LANCE the buffer length of 0 is
interpreted as a 4096-byte buffer. It is acceptable to
have a 0 length buffer on transmit with STP = 1 or
STP=1 andENP = 1. It is not acceptable to have 0
length buffer with STP = 0 and ENP =1.
If the OWN bit is set and the start of frame (STP) bit is
set, then microcode control proceeds to a routine that
will enable transmit data transfers to the FIFO. The
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| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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