參數(shù)資料
型號: AM79C974KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝: PLASTIC, QFP-132
文件頁數(shù): 98/153頁
文件大?。?/td> 838K
代理商: AM79C974KCW
AMD
P R E L I M I N A R Y
98
Am79C974
AC SWITCHING CHARACTERISTICS
SCSI Interface
FastClk Disabled (Control Register Three (0CH) bit 3=0), See Figure 29
Parameter
Symbol
t
PWL
1
t
CP
t
L
t
PWH
1
t
RISE
*
t
FALL
*
No.
1
2
3
4
5
6
Parameter Description
Clock Pulse Width Low
Clock Period (1
÷
Clock Frequency)
Synchronization Latency
Clock Pulse Width High
Clock Rise Time
Clock Fall Time
Test Conditions
Min
14.58
40
54.58
14.58
1
1
Max
Unit
ns
ns
ns
ns
V/ns
V/ns
0.65
t
CP
100
t
PWL
+ t
CP
0.65
t
CP
4
4
over 2 V p-p
over 2 V p-p
Notes:
1. For Synchronous data transmissions, the following condi-
tions must be true:
2t
CP
+ t
PWL
97.92 ns
2t
CP
+ t
PWH
97.92 ns
Clock Frequency Range for Fast Clk disabled.
=
10 MHz to 25 MHz for Asynchronous Transmission
=
12 MHz to 25 MHz for Synchronous Transmission
*
These parameters are not 100% tested, but are evalu-
ated at initial characterization and at any time the design
is modified where these parameters may be affected.
FastClk Enabled (Control Register Three (0CH) bit 3=1), See Figure 29
Parameter
Symbol
t
PWL
t
CP
t
L
t
PWH
t
RISE
*
t
FALL
*
No.
1
2
3A
4
5
6
Parameter Description
Clock Pulse Width Low
Clock Period (1
÷
Clock Frequency)
Synchronization Latency
Clock Pulse Width High
Clock Rise Time
Clock Fall Time
Test Conditions
Min
Max
0.6
t
CP
50
2
t
CP
0.6
t
CP
4
4
Unit
ns
ns
ns
ns
V/ns
V/ns
0.4
t
CP
25
54.58
0.4
t
CP
1
1
over 2 V p-p
over 2 V p-p
Notes:
Clock Frequency Range for Fast Clk enabled.
=
20 MHz to 40 MHz for Asynchronous Transmission
=
20 MHz to 40 MHz for Synchronous Transmission
*
These parameters are not 100% tested, but are evalu-
ated at initial characterization and at any time the design
is modified where these parameters may be affected.
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